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DS4830AT+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
Rev.1.20 Jan 27, 2006 page 5 of 27
REJ03B0069-0120
R8C/13 Group 1. Overview
Package: PLQP0032GB-A (32P6U-A)
Figure 1.3 Pin Assignments (Top View)
PIN Assignments (top view)
1 2 3 4 5 6 7 8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
9
2
8
2
7
2
6
2
5
2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7
3
2
3
1
3
0
R8C/13 Group
XI
N/
P
46
VS
S
R
E
S
E
T
V
C
C
C
N
VS
S
P
17/
I
N
T1/
C
N
T
R0
P
16/
C
L
K0
P15/RxD0
P
14/
T
x
D0
P
37/
T
x
D1
0/
R
x
D1
P
30/
C
N
T
R0/
C
M
P
10
P
33/
I
N
T3/
P
3
1/
T
ZO
U
T/
C
M
P
11
P
32/
I
N
T2/
C
N
T
R1/
C
M
P
12
I
VC
C
A
VS
S
A
VC
C/
VR
E
F
P
03/
A
N4
P02/AN5
P
01/
A
N6
P00/AN7/TxD11
P06/AN1
P
05/
A
N2
P04/AN3
P
45/
I
N
T0
P
10/
K
I0/
A
N8/
C
M
P
00
P11/KI1/AN9/CMP01
P
12/
K
I2/
A
N1
0/
C
M
P
02
P
13/
K
I3/
A
N1
1
P
07/
A
N0
M
O
D
E
T
CI
N
NOTES:
1. P4
7 functions only as an input port.
2. When using On-chip debugger, do not use P0
0/AN7/TxD11
and P37/TxD10/RxD1 pins.
3. Do not connect IVcc to Vcc.
XO
U
T/
P
47
(
1
)
(
3
)
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
Rev.1.20 Jan 27, 2006 page 6 of 27
REJ03B0069-0120
R8C/13 Group 1. Overview
Signal name Pin name I/O type
Power supply Vcc, I
input Vss
IVcc IVcc O
Analog power AVcc, AVss I
supply input
Reset input
___________
RESET I
CNVss CNVss I
MODE MODE I
Main clock input XIN I
Main clock output XOUT O
_____
INT interrupt input
_______ _______
INT0 to INT3 I
Key input interrupt
_____ _____
KI0 to KI3 I
input
Timer X CNTR0 I/O
__________
CNTR0 O
Timer Y CNTR1 I/O
Timer Z TZOUT O
Timer C TCIN I
CMP00 to CMP02,
O
CMP10 to CMP12
Serial interface CLK0 I/O
RxD0, RxD1 I
TxD0, TxD10,O
TxD11
Reference voltage VREF I
input
A/D converter AN0 to AN11 I
I/O port P00 to P07, I/O
P10 to P17,
P30 to P33, P37,
P45
Input port P46, P47 I
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generat-
ing circuit I/O. Connect a ceramic resonator or a crys-
tal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
The timer C output pins
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
Reference voltage input pin for A/D converter. Con-
nect the VREF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pull-
up resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Rev.1.20 Jan 27, 2006 page 7 of 27
REJ03B0069-0120
R8C/13 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and
FB comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
D
a
t
a
r
e
g
i
s
t
e
r
s
(
1
)
Address registers
(1)
F
r
a
m
e
b
a
s
e
r
e
g
i
s
t
e
r
s
(
1
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
I
n
t
e
r
r
u
p
t
t
a
b
l
e
r
e
g
i
s
t
e
r
User stack pointer
I
n
t
e
r
r
u
p
t
s
t
a
c
k
p
o
i
n
t
e
r
Static base register
F
l
a
g
r
e
g
i
s
t
e
r
N
O
T
E
S
:
1
.
A
r
e
g
i
s
t
e
r
b
a
n
k
c
o
m
p
r
i
s
e
s
t
h
e
s
e
r
e
g
i
s
t
e
r
s
.
T
w
o
s
e
t
s
o
f
r
e
g
i
s
t
e
r
b
a
n
k
s
a
r
e
p
r
o
v
i
d
e
d
R0H(High-order of R0)
b
1
5
b
8
b
7
b0
R
3
I
N
T
B
H
USP
I
S
P
SB
CDZSBOIU
I
P
L
R
0
L
(
L
o
w
-
o
r
d
e
r
o
f
R
0
)
R1H(High-order of R1)
R1L(Low-order of R1)
R
2
b
3
1
R3
R2
A1
A0
F
B
b
1
9
I
N
T
B
L
b
1
5
b0
P
C
b
1
9
b0
b15 b0
F
L
G
b
1
5
b0
b
1
5
b0 b
7
b8
Reserved bit
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
Figure 2.1 CPU Register
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

DS4830AT+

Mfr. #:
Buy DS4830AT+
Manufacturer:
Maxim Integrated
Description:
16-bit Microcontrollers - MCU ADVANCED OPTICAL UC BULK VERSION
Lifecycle:
New from this manufacturer.
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