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BU5255HFV-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Datasheet
www.rohm.com TSZ02201-0RFR1G200420-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
13/17
21.Oct.2013 Rev.001
TSZ22111･15･001
BU5255HFV BU5255SHFV
Power dissipation (total loss) indicates the power that the IC can consume at T
A
=25°C (normal temperature). As the IC
consumes power, it heats up, causing its temperature to be higher than the ambient temperature. The allowable
temperature that the IC can accept is limited. This depends on the circuit configuration, manufacturing process, and
consumable power.
Power dissipation is determined by the allowable temperature within the IC (maximum junction temperature) and the
thermal resistance of the package used (heat dissipation capability). Maximum junction temperature is typically equal to the
maximum storage temperature. The heat generated through the consumption of power by the IC radiates from the mold
resin or lead frame of the package. Thermal resistance, represented by the symbol θ
JA
°C/W, indicates this heat dissipation
capability. Similarly, the temperature of an IC inside its package can be estimated by thermal resistance.
Figure 26(a) shows the model of the thermal resistance of the package. The equation below shows how to compute for the
Thermal resistance (θ
JA
), given the ambient temperature (T
A
), maximum junction temperature (T
Jmax
), and power dissipation
(P
D
).
θ
JA
= (T
Jmax
-T
A
) / P
D
°C/W
The derating curve in Figure 26(b) indicates the power that the IC can consume with reference to ambient temperature.
Power consumption of the IC begins to attenuate at certain temperatures. This gradient is determined by Thermal
resistance (θ
JA
), which depends on the chip size, power consumption, package, ambient temperature, package condition,
wind velocity, etc. This may also vary even when the same of package is used. Thermal reduction curve indicates a
reference value measured at a specified condition. Figure 26(c) and (d) shows the derating curve for BU5255HFV and
BU5255SHFV.
When using the unit above T
A
=25°C, subtract the value above per Celsius degree. Permissible dissipation is the value
when FR4 glass epoxy board 70mm×70mm×1.6mm (copper foil area less than 3%) is mounted
5.4 mW/°C
0.0
0.2
0.4
0.6
0.8
0 25 50 75 100 125
Ambient Temperature [°C]
Power Dissipation [W]
Figure 26. Thermal Resistance and Derating Curve
0.0
0.2
0.4
0.6
0.8
0 25 50 75 100 125
Ambient Temperature [°C]
Power Dissipation [W]
BU5255HFV
BU5255SHFV
(c) BU5255HFV
(d) BU5255SHFV
85
105
(b) Derating Curve
A
mbient Temperature
T
C
]
Chip Surface Temperature T
J
[C]
(a) Thermal Resistance
[
θ
JA
=(T
Jmax
-T
A
)/P
D
C/W
0
A
mbient Temperature T
A
[C]
P2
P1
25 125
75 10050
Power Dissipation of LSI [W]
P
Dma
x
T
Jma
x
θ
JA2
θ
JA1
θ
JA2
<θ
JA1
Power Dissipation of IC
Datasheet
www.rohm.com TSZ02201-0RFR1G200420-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
14/17
21.Oct.2013 Rev.001
TSZ22111･15･001
BU5255HFV BU5255SHFV
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the P
D
stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum
rating, increase the board size and copper area to prevent exceeding the P
D
rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
Datasheet
www.rohm.com TSZ02201-0RFR1G200420-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
15/17
21.Oct.2013 Rev.001
TSZ22111･15･001
BU5255HFV BU5255SHFV
Operational Notes – continued
12. Regarding the Input Pin of the IC
In the construction of this IC, P-N junctions are inevitably formed creating parasitic diodes or transistors. The
operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical
damage. Therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an
input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when
no power supply voltage is applied to the IC. Even if the power supply voltage is applied, make sure that the input pins
have voltages within the values specified in the electrical characteristics of this IC.
13. Unused Circuits
When there are unused comparators, it is recommended that they are
connected as in Figure 27, setting the non-inverting input terminal to the
VDD, inverting input terminal to the VSS.
14. Input Voltage
Applying VDD+0.3V to the input terminal is possible without causing
deterioration of the electrical characteristics or destruction, regardless of
the supply voltage. However, this does not ensure normal circuit
operation. Please note that the circuit operates normally only when the
input voltage is within the common mode input voltage range of the
electric characteristics.
15. Power Supply(single/dual)
The voltage comparator operates when the voltage supplied is between VDD and VSS. Therefore, the single supply
voltage comparator can be used as dual supply voltage comparator as well.
16. Output Capacitor
If a large capacitor is connected between the output pin and VSS pin, current from the charged capacitor will flow into
the output pin and may destroy the IC when the VDD pin is shorted to ground or pulled down to 0V. Use a capacitor
smaller than 0.1µF between output pin and VSS pin.
17. Oscillation by Output Capacitor
Please pay attention to the oscillation by output capacitor and in designing an application of negative feedback loop
circuit with these ICs.
18. Latch up
Be careful of input voltage that exceed the VDD and VSS. When CMOS device have sometimes occur latch up and
protect the IC from abnormaly noise.
Figure 27. Example of Application Circuit
for Unused Comparator
VSS
VDD
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

BU5255HFV-TR

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Analog Comparators Super Fast Recovery Diode
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