NCP1200
www.onsemi.com
13
Improving the Output Drive Capability
The NCP1200 features an asymmetrical output stage used
to soften the EMI signature. Figure 25 depicts the way the
driver is internally made:
V
CC
2
3
1
5
7
Q
Q\
Figure 25. The higher ON resistor slows down
the MOSFET while the lower OFF resistor
ensures fast turnoff.
40
12
In some cases, it is possible to expand the output drive
capability by adding either one or two bipolar transistors.
Figures 26, 27, and 28 give solutions whether you need to
improve the turnon time only, the turnoff time or both. Rd
is there to damp any overshoot resulting from long copper
traces. It can be omitted with short connections. Results
showed a rise fall time improvement by 5X with standard
2N2222/2N2907:
NCP1200
1
2
3
4
8
7
6
5
2N2907
2N2222
To Gate
Rd
Figure 26. Improving Both TurnOn and
TurnOff Times
NCP1200
1
2
3
4
8
7
6
5
2N2907
1N4148
To Gate
Figure 27. Improving TurnOff Time Only
6
NCP1200
1
2
3
4
8
7
5
2N2222
To Gate
1N4148
Figure 28. Improving TurnOn Time Only
NCP1200
www.onsemi.com
14
If the leakage inductance is kept low, the MTD1N60E can
withstand accidental avalanche energy, e.g. during a
highvoltage spike superimposed over the mains, without
the help of a clamping network. If this leakage path
permanently forces a drainsource voltage above the
MOSFET BVdss (600 V), a clamping network is mandatory
and must be built around Rclamp and Clamp. Dclamp shall
react extremely fast and can be a MUR160 type. To calculate
the component values, the following formulas will help you:
R
clamp
=
2 @ V
clamp
@ (V
clamp
* (V
out
) Vf sec) @ N)
L
leak
@ Ip
2
@ Fsw
C
clamp
+
V
clamp
V
ripple
@ Fsw @ R
clamp
with:
V
clamp
: the desired clamping level, must be selected to be
between 40 V to 80 V above the reflected output voltage
when the supply is heavily loaded.
V
out
+ Vf: the regulated output voltage level + the secondary
diode voltage drop
L
leak
: the primary leakage inductance
N: the Ns:Np conversion ratio
F
SW
: the switching frequency
V
ripple
: the clamping ripple, could be around 20 V
Another option lies in implementing a snubber network
which will damp the leakage oscillations but also provide
more capacitance at the MOSFET’s turnoff. The peak
voltage at which the leakage forces the drain is calculated
by:
V
max
+ Ip @
L
leak
C
lump
Ǹ
where C
lump
represents the total parasitic capacitance seen
at the MOSFET opening. Typical values for Rsnubber and
Csnubber in this 4W application could respectively be 1.5
kW and 47 pF. Further tweaking is nevertheless necessary to
tune the dissipated power versus standby power.
Available Documents
“Implementing the NCP1200 in Lowcost ACDC
Converters”, AND8023/D.
“Conducted EMI Filter Design for the NCP1200’’,
AND8032/D.
“Ramp Compensation for the NCP1200’’, AND8029/D.
TRANSient and AC models available to download at:
http://onsemi.com/pub/NCP1200
NCP1200 design spreadsheet available to download at:
http://onsemi.com/pub/NCP1200
ORDERING INFORMATION
Device Type Marking Package Shipping
NCP1200P40G
F
SW
= 40 kHz
1200P40 PDIP8
(PbFree)
50 Units / Rail
NCP1200D40R2G 200D4 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1200P60G
F
SW
= 60 kHz
1200P60 PDIP8
(PbFree)
50 Units / Rail
NCP1200D60R2G 200D6 SOIC8
(PbFree)
2500 / Tape & Reel
NCP1200P100G
F
SW
= 100 kHz
1200P100 PDIP8
(PbFree)
50 Units / Rail
NCP1200D100R2G 200D1 SOIC8
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1200
www.onsemi.com
15
PACKAGE DIMENSIONS
PDIP8
P SUFFIX
CASE 62605
ISSUE N
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A −−−− 0.210
A1 0.015 −−−−
b 0.014 0.022
C 0.008 0.014
D 0.355 0.400
D1 0.005 −−−−
e 0.100 BSC
E 0.300 0.325
M −−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L 0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2
A2
NOTE 3
M
B
M
NOTE 6
M

NCP1200P60G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 60KHz Current Mode SMPS PWM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union