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ICS91720BGLF

P1-P3P4-P6P7-P9P10-P11
Integrated
Circuit
Systems, Inc.
ICS91720
0698D—10/05/04
Block Diagram
Pin Configuration
Features:
• ICS91720 is a Spread Spectrum Clock targeted for
Mobile PC and LCD panel applications that
generates an EMI-optimized clock signal (EMI peak
reduction of 7-14 dB on 3rd-19th harmonics) through
use of Spread Spectrum techniques.
• ICS91720 focuses on the lower input frequency
range of 14.318 to 80.00 MHz with a spread
modulation of 20kHz to 40kHz.
Specifications:
• Supply Voltages: V
DD
= 3.3V ±0.3V
• Frequency range: 14.318 MHz ≤ Fin ≥ 80 MHz
• Cyc to Cyc jitter: <150ps
• Output duty cycle 45-55%
• Guarantees +85°C operational condition.
• 8-pin SOIC/TSSOP
• Reference input
Low EMI, Spread Modulating, Clock Generator
Functionality
CLK
CL
REFOUT
K
OUT
OUT
PD#
PD#
CLKIN
CLKIN
PLL1
PLL1
Spread
Spread
Spectr
Spectr
um
um
SD
SD
ATA
SCLK
SCLK
FS_IN0:1
Control
Control
Logic
Logic
Config.
Config.
Reg.
Reg.
CLKIN
18
PD#*
VDD
27
SCLK
GND
36
SDATA
**
CLKOUT/FS_IN0
45
REF_OUT/FS_IN1
*
** Internal Pull-Down Resistor
8 Pin SOIC/TSSOP
* Internal Pull-Up Resistor
FSIN_1 FSIN_0
0 0 -0.8 down spread
0 1 -1.00 down spread
1 0 27.00MHz in --> 27.00MHz out -1.25 down spread
1 1 -0.8 down spread48.00MHz in -->48.00 MHz out
MHz Spread % default
14.318 MHz in --> 27MHz out
14.318MHz -->14.318MHz out
2
ICS91720
0698D—10/05/04
Pin Description
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1CLKIN PWRIn
p
ut for reference clock.
2 VDD IN Power su
pp
l
y
, nominal 3.3V
3 GND OUT Ground
p
in.
Modulated clock out
p
ut.
Fre
q
uenc
y
select latch in
p
ut. Refer to the functionalit
y
table.
Un-modulated 3.3V reference clock out
p
ut.
Fre
q
uenc
y
select latch in
p
ut. Refer to the functionalit
y
table.
6 SDATA PWR Data
p
in for I2C circuitr
y
5V tolerant
7 SCLK PWR Clock
in of I2C circuitr
5V tolerant
8PD#* PWR
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
I/O
I/O
4 **CLKOUT/FS_IN0
REF_OUT/FS_IN1*5
3
ICS91720
0698D—10/05/04
Table 1: Frequency Configuration Table
(See I2C Byte 0)
Above is the hard coded 5 bit (32 entry) ROM table.
FS2:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS3 and FS4 can also be
decoded from FS_IN0:1 latched input hardware pins.
FS_IN0 → FS3 and FS_IN1 → FS4. Upon power-up the default is to use hardware selections of FS_IN0:1 latched
values.
FS2 = 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).
To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power
up default of FS_IN1:0 = 10 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software
selection by switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %
00000 0.60
00001 0.80
00010 1.00
00011 1.25
00100 1.50
00101 2.00
00110 0.50
00111 1.00
01000 0.60
01001 1.00
0 1 0 1 0 -0.80
0 1 0 1 1 CNTR SPD +/-0.3
01100 1.50
01101 1.75
01110 2.00
01111 2.50
10000 3.00
10001 -1.25
10010 0.40
10011 0.50
10100 0.70
10101 1.00
10110 1.20
10111 1.50
11000 0.60
11001 0.80
11010 1.00
11011 1.25
11100 1.50
11101 2.00
11110 0.50
11111 1.00
48in/48out
66in/66out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/27out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/14out
27in/27out
DOWN
SPREAD
(-)
DOWN
SPREAD
(-)
CENTER
SPREAD
(+/-)
P1-P3P4-P6P7-P9P10-P11

ICS91720BGLF

Mfr. #:
Buy ICS91720BGLF
Manufacturer:
Description:
IC CLK GENERATOR LOW EMI 8-TSSOP
Lifecycle:
New from this manufacturer.
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