LTC6406
20
6406fc
Layout Considerations
Because the LTC6406 is a very high speed amplifi er, it is
sensitive to both stray capacitance and stray inductance.
In the QFN package, three pairs of power supply pins are
provided to keep the power supply inductance as low
as possible to prevent any degradation of amplifi er 2nd
harmonic performance. It is critical that close attention be
paid to supply bypassing. For single supply applications
it is recommended that high quality 0.1μF surface mount
ceramic bypass capacitor be placed directly between each
V
+
and V
–
pin with direct short connections. The V
–
pins
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it is
recommended that additional high quality, 0.1μF ceramic
capacitors are used to bypass V
+
to ground and V
–
to
ground, again with minimal routing. For driving large loads
(<200Ω), additional bypass capacitance may be needed for
optimal performance. Keep in mind that small geometry
(e.g. 0603) surface mount ceramic capacitors have a much
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
Any stray parasitic capacitances to ground at the summing
junctions, +IN and –IN, should be minimized. This becomes
especially true when the feedback resistor network uses
resistor values >500Ω in circuits with R
F
= R
I
. Excessive
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around R
F
.
Always keep in mind the differential nature of the LTC6406,
and that it is critical that the load impedances seen by both
outputs (stray or intended), should be as balanced and
symmetric as possible. This will help preserve the natural
balance of the LTC6406, which minimizes the generation
of even order harmonics, and improves the rejection of
common mode signals and noise.
It is highly recommended that the V
OCM
pin be bypassed
to ground with a high quality ceramic capacitor whose
value exceeds 0.01μF. This will help stabilize the common
mode feedback loop as well as prevent thermal noise from
the internal voltage divider and other external sources of
noise from being converted to differential noise due to
divider mismatches in the feedback networks. It is also
recommended that the resistive feedback networks be
comprised of 1% resistors (or better) to enhance the
output common mode rejection. This will also prevent
V
OCM
input referred common mode noise of the common
mode amplifi er path (which cannot be fi ltered) from being
converted to differential noise, degrading the differential
noise performance.
Feedback factor mismatch has a weak effect on distortion.
Using 1% or better resistors will limit any mismatch from
impacting amplifi er linearity. However, in single supply
level-shifting applications where there is a voltage differ-
ence between the input common mode voltage and the
output common mode voltage, resistor mismatch can
make the apparent voltage offset of the amplifi er appear
worse than specifi ed.
Interfacing the LTC6406 to A/D Converters
Rail-to-rail input and fast settling time make the LTC6406
ideal for interfacing to low voltage, single supply, differ-
ential input ADCs. The sampling process of ADCs create
a sampling glitch caused by switching in the sampling
capacitor on the ADC front end which momentarily “shorts”
the output of the amplifi er as charge is transferred between
the amplifi er and the sampling capacitor. The amplifi er
must recover and settle from this load transient before this
acquisition period ends for a valid representation of the
input signal. In general, the LTC6406 will settle much more
quickly from these periodic load impulses than from a 2V
input step, but it is a good idea to either use the fi ltered
outputs to drive the ADC (Figure 11 shows an example
of this), or to place a discrete R-C fi lter network between
the differential unfi ltered outputs of the LTC6406 and the
input of the ADC to help absorb the charge injection that
comes out of the ADC from the sampling process. The
capacitance of the fi lter network serves as a charge reservoir
to provide high frequency charging during the sampling
process, while the two resistors of the fi lter network are
used to dampen and attenuate any charge kickback from
the ADC. The selection of the R-C time constant is trial
and error for a given ADC, but the following guidelines
are recommended: Choosing too large of a resistor in the
decoupling network leaving insuffi cient settling time will
create a voltage divider between the dynamic input imped-
ance of the ADC and the decoupling resistors. Choosing
too small of a resistor will possibly prevent the resistor
APPLICATIONS INFORMATION
