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SC4809BIMSTRT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
102005 Semtech Corp. www.semtech.com
SC4809A/B/C
POWER MANAGEMENT
The primary inductance can be calculated given an
acceptable current ripple, ∆I
L
.
∆I
L
was set to equal one-
half the peak primary current. For a CCM flyback design,
the peak primary current is calculated:
2
I
D1
1
N
I
I
L
max
(max)OUT
PEAK
∆
+
−
•
=
Because the converter is operating in the continuous
mode, the maximum peak flux density B
MAX
, is limited by
the saturation flux density, B
SAT
. Taking all this into
consideration, the maximum core size is determined by.
31.1
MAX
4
RMSPEAKP
Bk420
10IIL
AP
••
•••
=
where AP = the core area product in cm
4
,
k = winding factor,
B
MAX
≈ B
SAT
,
The result is compared to the product of the winding area,
Aw (cm
2
), and effective core area, Ae (cm
2
), listed in the
core manufacturer’s data sheet.
The minimum number of primary turns is determined by:
AeB
10IL
N
MAX
4
PEAKP
P
•
••
=
Based upon this result and the predetermined turns ratio,
the number of secondary turns is established.
The energy stored in the flyback transformer is actually
stored in an air gap in the core. This is because the high
permeability of the ferrite material can’t store much
energy without saturating first. By adding an air gap, the
hysteresis curve of the magnetic material is actually tilted,
requiring a much higher field strength to saturate the
core. The length of the air gap is calculated by:
P
22
Pro
g
L
10Ae)N(
−
•••µ•µ
=l
Application Information (Cont.)
MOSFET Selection
The switching element in a flyback converter must have
a voltage rating high enough to handle the maximum input
voltage and the reflected secondary voltage, not to
mention any leakage inductance induced spike that is
inevitably present. Approximate the required voltage
rating of the MOSFET using.
()
()
3.1VV
N
N
VVV
DO
S
P
L(max)INds
•
+•
++=
where V
ds
= the required drain to source voltage rating of
the MOSFET,
V
L
= the voltage spike due to the leakage inductance of
the transformer, estimated to be thirty percent of V
IN(MAX)
,
and the additions 1.3 factor includes an overall thirty
percent margin.
This FET will experience both switching and conduction
losses. The conduction losses will be equal to the I
2
R
losses, as shown by:
()
)ON(DS
2
RMSCOND
RIP •=
Switching losses are the result of overlapping drain
current and drain to source voltage at turn on and turn
off.
The total switching losses are estimated based on
equation:
swchPEAKDS
SW
2
DSOSS
SW
ftIV
2
f)V(C
P •••+
••
=
where t
ch
:
)th(gs
ggd
CH
VVDD
RQ
t
−
•
=
Diode Selection
Schottky rectifiers have a lower forward voltage drop than
typical PN devices, making it the rectifier of choice when
considering reducing converter losses and improving
overall efficiency. Selecting the appropriate Schottky for
a specific application depends mainly on the working
peak reverse voltage rating and peak repetitive forward
current.
112005 Semtech Corp. www.semtech.com
SC4809A/B/C
POWER MANAGEMENT
Input and Output Capacitors
The input capacitors are chosen based upon their ripple
current rating and their rated voltage. The actual capacitor
value is not that critical as long as the minimum
capacitance gives an acceptable ripple voltage
determined by the following equation:
Vf8
I
C
SW
RMS
MIN
∆••
=
The output capacitors are also chosen based upon their
low equivalent series resistance (ESR), ripple current and
voltage ratings. The ripple current that the output
capacitor experiences is a result of supplying the load
current during the FET conduction time and its charging
current during the FET off-time.
Voltage Feedback
The FB pin of the SC4809 sums the voltage feedback
signal to the current sense signal and any added slope
compensation. The voltage feedback signal is from an
optocoupler, which is driven from an error amplifier on
the secondary side of the converter. The signal from the
optocoupler is designed to trip the FB threshold of the
SC4809 internal comparator when the output voltage
exceeds its specified limit.
Current Limit
Selection of the current sense resistor is accomplished
by dividing the FB threshold value by the peak primary
current at the desired current limit point. This ground-
referenced R
SENSE
must be a low inductance type and have
a rated power level to meet the (I
RMS
)
2
• R
SENSE
requirement.
Current spikes caused by the leakage inductance of the
flyback transformer and the reverse recovery of the diode
could trip the current sense latch and prematurely shut
off the output. This unwanted spike can be suppressed
by adding a small RC filter for effective leading edge
blanking.
Slope Compensation
Sensing peak inductor current instead of average
inductor current results in a loop response that is Less
than ideal. Adding slope compensation to the current
signal cancels this error by maintaining a constant average
current independent of duty cycle. Slope compensation
is required for open loop stability in a current mode system
with 50% or greater duty cycles, but will benefit any
current mode application at the cost of a few small parts.
Loop Compensation
The continuous current mode flyback will contain a right-
half-plane (RHP) zero in its transfer function. Any increase
in load current will require the primary peak inductor
current to increase. The duty cycle must increase to
accomplish this. In a flyback converter, the inductor
current flows to the output only when the FET is off and
the diode is conducting. Increasing the duty cycle
increases the FET condition time but decreases the diode
conduction time. The result of this is the average diode
current, the current that supplies the load, actually
decreases. This is a temporary situation; as the inductor
current rises, the diode current eventually reaches its
proper value. The condition where the average diode
current must actually decrease before it can increase is
referred to as a right-half-plane zero. To complicate
matters, this zero contributes a phase lag, not a phase
lead as a normal zero would. This zero moves in frequency
as a function of load and input voltage, making it
impossible to cancel out by the insertion of a pole.
)VNV(LR2
VN
f
OUTINPOUT
2
IN
RHPZERO
•+•••π•
•
=
The easiest way to deal with a right-half-plane zero is to
roll off the loop gain at a relatively low frequency using
simple dominant pole compensation. Unfortunately, the
result of this is poor dynamic response.
The primary goal of the compensation network is to
provide good line and load regulation and dynamic
response. These objectives are best met by providing
high gain at low frequencies for good DC regulation and
high bandwidth for good transient response. Optimum
closed loop performance can only be achieved by first
Application Information (Cont.)
122005 Semtech Corp. www.semtech.com
SC4809A/B/C
POWER MANAGEMENT
knowing what the transfer characteristic of the PWM and
switching circuit looks like. Constructing a Bode plot of
the known poles and zeros in the power stage does this.
Bode plots give a visual interpretation of the gain versus
frequency and phase versus frequency characteristics
of a system. In the gain plot, the gain shown at each
frequency represents the amount by which the feedback
loop will reduce a disturbance at that frequency.
Besides the RHP zero, the output capacitor and the load
contribute a pole and the output capacitor alone will
contribute a zero based upon its ESR.
OUTOUT
pole
CR2
D1
f
••π•
+
=
OUT
zero
CESR2
1
f
••π
=
The control to output gain is calculated by:
+•••−•
••
••=
)VVN2()D1(V
VRI
log20GAIN
INOC
INOUTSC
Once the frequency response of the uncompensated
system is determined, the next step is to determine what
compensation is needed around the error amplifier for
optimum performance. As stated earlier, optimum
performance requires a high gain at low frequencies for
good DC regulation and high bandwidth for good transient
response. The crossover frequency, f
c
, is the frequency
at which the gain magnitude equals 0dB. High bandwidth
is achieved by having the highest possible f
c
. Because of
the RHP zero, the highest possible crossover frequency
is limited to f
RHPZERO
/π. The phase margin, or the amount
the phase lag measures at f
c
less 180°, should be at
least 45° for good transient response with little
overshoot. The magnitude of the gain at the frequency
where the phase plot measures - 180° is referred to as
the gain margin. If the slope of the gain plot is -2, or
-40dB/decade, at low frequencies, it much transition to
a -20dB/decade slope, also known as a -1 slope, one
decade before crossing the 0dB point. If the slope
remains at the -2 slope the resultant gain margin would
be too small causing sever underdamped oscillations at
fc.
Application Information (Cont.)
The scheme shown below will handle most compensation
requirements. There is a pole at the origin which
contributes a -1 slope in the gain plot, a low frequency
zero, f
EAZERO
flattens out the slope so the mid-range gain
is equal to Rf/Ri. A high frequency pole, f
EAPOLE
helps
suppress any high frequency noise from propagating
through the system. Rd forms a voltage divider with Ri
and provides a DC offset.
pf
EAPOLE
ff
EAZERO
CR2
1
f
CR2
1
f
••π•
=
••π•
=
By combining the Bode plots of the PWM and power stage
with the error amplifier compensation, a plot of the entire
system is realized.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

SC4809BIMSTRT

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Buy SC4809BIMSTRT
Manufacturer:
Semtech
Description:
Switching Controllers HG PERFORMANCE CUR MODE PWM CN
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