© Semiconductor Components Industries, LLC, 2016
August, 2016 Rev. 14
1 Publication Order Number:
MC10LVEP11/D
MC10LVEP11, MC100LVEP11
2.5V / 3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC10/100LVEP11 is a differential 1:2 fanout buffer. The
device is pin and functionally equivalent to the EP11 device. With AC
performance the same as the EP11 device, the LVEP11 is ideal for
applications requiring lower voltage. Single-ended CLK input
operation is limited to a V
CC
w 3.0 V in PECL mode, or V
EE
v
3.0 V in NECL mode.
The 100 Series contains temperature compensation.
Features
240 ps Typical Propagation Delay
Maximum Frequency > 3.0 GHz Typical
PECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= 2.375 V to 3.8 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at V
EE
LVDS Input Compatible
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5X = MC10 Y= Year
4K = MC100 W = Work Week
M
= Date Code
G = Pb-Free Package
ALYWG
G
HU11
ALYWG
G
KU11
1
8
1
8
www.onsemi.com
HVP11
ALYW
G
1
8
KVP11
ALYW
G
1
8
5X MG
G
14
(Note: Microdot may be in either location)
4K MG
G
14
*For additional marking information, refer to
Application Note AND8002/D
.
SOIC8NB
D SUFFIX
CASE
75107
TSSOP8
DT SUFFIX
CASE
948R02
1
8
1
8
DFN8
MN SUFFIX
CASE 506AA
MARKING DIAGRAMS*
See detailed ordering and shipping information on page 9 of
this data sheet.
ORDERING INFORMATION
MC10LVEP11, MC100LVEP11
www.onsemi.com
2
1
2
3
45
6
7
8
D
V
EE
V
CC
Q0
DQ1
Q1
Q0
Figure 1. 8-Lead Pinout (Top View) and Logic
Diagram
Table 1. PIN DESCRIPTION
PIN FUNCTION
D*, D** ECL Data Inputs
Q0, Q0, Q1, Q1 ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient ther-
mal conduit. Electrically connect to the
most negative supply (GND) or leave
unconnected, floating open.
*Pins will default to 2/3 V
CC
when left open.
**Pins will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8NB
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Transistor Count 110 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC10LVEP11, MC100LVEP11
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V 6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6
6
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC8NB 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC8NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8 129
84
°C/W
T
sol
Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)

MC100LVEP11DTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V ECL 1:2 Diff Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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