AT87F55WD-24JC Datasheet AT87F55WD-24AI, AT87F55WD-24JC, AT87F55WD-24JI | P13-P15

AT87F55WD

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on

P1.0, as shown in Figure 9. This pin, besides being a regu-

lar I/O pin, has two alternate functions. It can be pro-

grammed to input the external clock for Timer/Counter 2 or

to output a 50% duty cycle clock ranging from 61 Hz to

4 MHz at a 16 MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

C/T2

(T2CON.1) must be cleared and bit T2OE (T2MOD.1)

must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer 2

as a baud-rate generator and a clock generator simulta-

neously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from one

another since they both use RCAP2H and RCAP2L.

Interrupts

The AT87F55WD has a total of six interrupt vectors: two

external interrupts (INT0

and INT1), three timer interrupts

(Timers 0, 1, and 2), and the serial port interrupt. These

interrupts are all shown in Figure 10.

Each of these interrupt sources can be individually enabled

or disabled by setting or clearing a bit in Special Function

disables all interrupts at once.

Note that Table 5 shows that bit position IE.6 is unimple-

mented. In the AT87F55WD, bit position IE.5 is also unim-

plemented. User software should not write 1s to these bit

positions, since they may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2

and EXF2 in register T2CON. Neither of these flags is

cleared by hardware when the service routine is vectored

to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at

S5P2 of the cycle in which the timers overflow. The values

are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the

same cycle in which the timer overflows.

Table 6. Interrupt Enable (IE) Register

Figure 10. Interrupt Sources

Clock-out Frequency

Oscillator Frequency

4 x [65536-(RCAP2H,RCAP2L)]

-------------------------------------------------------------------------------------=

(MSB) (LSB)

EA – ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0,

no interrupt is acknowledged. If

EA = 1, each interrupt source is

individually enabled or disabled

by setting or clearing its enable

bit.

– IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit

ES IE.4 Serial Port interrupt enable bit

ET1 IE.3 Timer 1 interrupt enable bit

EX1 IE.2 External interrupt 1 enable bit

ET0 IE.1 Timer 0 interrupt enable bit

EX0 IE.0 External interrupt 0 enable bit

User software should never write 1s to unimplemented bits,

because they may be used in future AT87 products.

IE1

IE0

TF1

TF0

INT1

INT0

TF2

EXF2

AT87F55WD

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 11. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven, as shown in Figure 12.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invokes idle mode should not write to a port pin or to exter-

nal memory.

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the

instruction that invokes power-down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode is termi-

nated. Exit from power-down can be initiated either by a

hardware reset or by an enabled external interrupt. Reset

redefines the SFRs but does not change the on-chip RAM.

The reset should not be activated before V

is restored to

its normal operating level and must be held active long

enough to allow the oscillator to restart and stabilize.

Figure 11. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 12. External Clock Drive Configuration

XTAL2

GND

XTAL1

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Table 7. Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

AT87F55WD

Program Memory Lock Bits

The AT87F55WD has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value and holds that value until reset is activated. The

latched value of EA

must agree with the current logic level

at that pin in order for the device to function properly.

Programming the QuickFlash

The AT87F55WD is shipped with the on-chip QuickFlash

memory array ready to be programmed. The programming

interface needs a high-voltage (12-volt) program enable

signal and is compatible with conventional third-party Flash

or EPROM programmers.

The AT87F55WD code memory array is programmed byte-

by-byte.

Programming Algorithm: Before programming the

AT87F55WD, the address, data, and control signals should

be set up according to the QuickFlash programming mode

table and Figure 13 and Figure 14. To program the

AT87F55WD, take the following steps:

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA

to 12V.

5. Pulse ALE/PROG

once to program a byte in the

QuickFlash array or the lock bits. The byte-write

cycle is self-timed and typically takes no more than

50 µs. Repeat steps 1 through 5, changing the

address and data for the entire array or until the end

of the object file is reached.

Data

Polling: The AT87F55WD features Data Polling to

indicate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written data on P0.7. Once the write cycle

has been completed, true data is valid on all outputs, and

the next cycle may begin. Data

Polling may begin any time

after a write cycle has been initiated.

Ready/Busy

: The progress of byte programming can also

be monitored by the RDY/BSY

output signal. P3.0 is pulled

low after ALE goes high during programming to indicate

BUSY

. P3.0 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 000H, 100H, and 200H, except that P3.6 and

P3.7 must be pulled to a logic low. The values returned are

as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 87H indicates 87F family

(200H) = 05H indicates 87F55WD

Table 8. Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features

2PUU

MOVC instructions executed

from external program

memory are disabled from

fetching code bytes from

internal memory, EA

sampled and latched on reset,

and further programming of

the QuickFlash memory is

disabled.

3PPU

Same as mode 2, but verify is

also disabled

4PPP

Same as mode 3, but external

execution is also disabled

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

AT87F55WD-24JC

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AT87F55WD-24JC

AT87F55WD-24JC

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