10
FN6755.2
September 25, 2015
Interrupt Control Register (INT) [Address 0Eh]
OSCILLATOR ENABLE BIT (EOSC)
The EOSC
bit enables the crystal oscillator function when it
is set to “0”. When the EOSC
bit is set to “1”, the crystal
oscillator function is disabled, and the device enters power-
saving mode. The EOSC
bit is set to “0” at power-up.
FREQUENCY OUT CONTROL BITS (RS2, RS1)
These bits select the output frequency at the IRQ1
/F
OUT
pin. INTCN must be set to “0” for frequency output at the
IRQ1
/F
OUT
pin. See Table 3 for Frequency Selection of the
F
OUT
pin.
INTERRUPT CONTROL BIT (INTCN) AND ALARM
INTERRUPT ENABLE BITS (A2IE, A1IE)
The INTCN bit controls the relationship between the alarm
interrupts and the IRQ1
/F
OUT
and IRQ2 pins. The A2IE and
A1IE bits enable the alarm interrupts, A2F and A1F, to assert
the IRQ1
/F
OUT
and IRQ2 pins. See Table 4 for Alarm
Interrupt Selection with INTCN, A2IE and A1IE bits.
Status Register (SR) [Address 0Fh]
The Status Register is located in the memory map at
address 0Fh. This is a volatile register that provides status of
oscillator failure and alarm interrupts.
ALARM1 INTERRUPT BIT (A1F)
These bits announce if the Alarm1 matches the real-time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not to “1”.
ALARM2 INTERRUPT BIT (A2F)
These bits announce if the Alarm2 matches the real-time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not to “1”.
OSCILLATOR FAILURE BIT (OSF)
This bit is set to a “1” when there is no oscillation on the X1
pin. The bit is set by hardware (ISL12057 internally) and can
only be disabled by having an oscillation on X1 and manually
resetting to “0” to reset it.
Alarm1 Registers
Addresses [Address 07h to 0Ah]
The Alarm1 register bytes are set up identically to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. When all the enable bits are set to “1”,
Alarm1 triggers once per second. Note that there is no alarm
byte for month and year.
The Alarm1 function works as a comparison between the
Alarm1 registers and the RTC registers. As the RTC
advances, Alarm1 is triggered when a match occurs
between the Alarm1 registers and the RTC registers. Any
one Alarm1 register, multiple registers, or all registers can be
enabled for a match.
To clear Alarm1, the A1F status bit must be set to “0” with a
write.
TABLE 2. INTERRUPT CONTROL REGISTER (INT)
ADDR76543210
0Eh EOSC
0 0 RS2 RS1 INTCN A2IE A1IE
Default00011000
TABLE 3. FREQUENCY SELECTION OF
F
OUT
PIN
FREQUENCY
F
OUT
(Hz) RS2 RS1 COMMENT
32768 1 1 Free-running crystal clock
8192 1 0 Free-running crystal clock
4096 0 1 Free-running crystal clock
1 0 0 Sync at RTC write
TABLE 4. ALARM INTERRUPT SELECTION WITH INTCN,
A2IE AND A1IE BITS
INTCN A2IE A1IE IRQ1
/F
OUT
IRQ2
000 F
OUT
HIGH
001 F
OUT
A1F
010 F
OUT
A2F
011 F
OUT
A1F or A2F
1 0 0 HIGH HIGH
101 HIGH A1F
110 A2F HIGH
1 1 1 A2F A1F
TABLE 5. STATUS REGISTER (SR)
ADDR 7 6 5 4 3 2 1 0
0Fh OSF 0 0 0 0 0 A2F A1F
Default 1 0 0 0 0 0 0 0
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS
SELECTION
A1DW/DT
A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT
X 1111 Every Second
X 0111 Match Second
X 1011 Match Minute
ISL12057
