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NLV14017BDR2G

P1-P3P4-P6P7-P8
MC14017B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(Note 6)
Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time
Reset to Decode Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 415 ns
t
PLH
, t
PHL
= (0.66 ns/PF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 150 ns
t
PLH
,
t
PHL
5.0
10
15
−
−
−
500
230
175
1000
460
350
ns
Propagation Delay Time
Clock to C
out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 315 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 142 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 100 ns
t
PLH
,
t
PHL
5.0
10
15
−
−
−
400
175
125
800
350
250
ns
Propagation Delay Time
Clock to Decode Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 415 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 150 ns
t
PLH
,
t
PHL
5.0
10
15
−
−
−
500
230
175
1000
460
350
ns
Turn−Off Delay Time
Reset to C
out
t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PLH
= (0.66 ns/pF) C
L
+ 142 ns
t
PLH
= (0.5 ns/pF) C
L
+ 100 ns
t
PLH
5.0
10
15
−
−
−
400
175
125
800
350
250
ns
Clock Pulse Width t
w(H)
5.0
10
15
250
100
75
125
50
35
−
−
−
ns
Clock Frequency f
cl
5.0
10
15
−
−
−
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width t
w(H)
5.0
10
15
500
250
190
250
125
95
−
−
−
ns
Reset Removal Time t
rem
5.0
10
15
750
275
210
375
135
105
−
−
−
ns
Clock Input Rise and Fall Time t
TLH
,
t
THL
5.0
10
15
No Limit
−
Clock Enable Setup Time t
su
5.0
10
15
350
150
115
175
75
52
−
−
−
ns
Clock Enable Removal Time t
rem
5.0
10
15
420
200
140
260
100
70
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14017B
http://onsemi.com
5
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
V
DD
V
out
V
SS
V
DD
V
SS
S1
S1
A
B
V
SS
I
D
EXTERNAL
POWER
SUPPLY
CLOCK
ENABLE
RESET
CLOCK
C
out
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Output
Sink Drive
Output
Source Drive
Decode
Outputs
Clock to
desired
outputs
(S1 to B)
(S1 to A)
Carry
Clock to 5
thru 9
(S1 to B)
S1 to A
V
GS
=− V
DD
V
DD
V
DS
=V
out
− V
DD
V
out
Figure 2. Typical Power Dissipation Test Circuit
V
DD
V
SS
I
D
CLOCK
ENABLE
RESET
CLOCK
C
out
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
500 mF
0.01 mF
CERAMIC
PULSE
GENERATOR
f
c
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
MC14017B
http://onsemi.com
6
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 3. Counter Expansion
RESET
CLOCK
CE
MC14017B
Q0 Q1 Q8 Q9
•••
9 DECODED
OUTPUTS
CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
RESET
CLOCK
CE
MC14017B
Q0Q1 Q8 Q9
•••
RESET
CLOCK
CE
MC14017B
Q1 Q8 Q9
•••
8 DECODED
OUTPUTS
8 DECODED
OUTPUTS
Figure 4. AC Measurement Definition and Functional Waveforms
Pcp
Ncp
CLOCK
CLOCK
ENABLE
t
rem
RESET
20 ns
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
C
out
t
PHL
t
PHL
t
PLH
t
PLH
t
PLH
t
PLH
t
PLH
t
PLH
t
THL
t
THL
t
TLH
t
PLH
t
PLH
t
PLH
t
TLH
t
PLH
t
PHL
t
PHL
t
PHL
t
PHL
50%
t
PHL
t
PHL
90%
10%
t
THL
t
PHL
t
THL
t
PHL
t
THL
t
TLH
t
THL
t
PHL
t
rem
t
su
20 ns
20 ns
20 ns20 ns
t
PLH
90%
10%
50%
t
TLH
t
TLH
t
TLH
t
TLH
t
TLH
t
THL
t
THL
t
THL
t
THL
t
PHL
t
THL
90%
50%
10%
20 ns
t
PLH
t
TLH
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
P1-P3P4-P6P7-P8

NLV14017BDR2G

Mfr. #:
Buy NLV14017BDR2G
Manufacturer:
ON Semiconductor
Description:
Multipliers / Dividers DECADE COUNTER/DIVIDER
Lifecycle:
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