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MAX9381ESA+T

P1-P3P4-P6P7-P7
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
4 _______________________________________________________________________________________
Typical Operating Characteristics
(V
CC
- V
EE
= 3.3V, outputs loaded with 50Ω ±1% to V
CC
- 2V, V
IH
= V
CC
- 1V, V
IL
= V
CC
- 1.5V, f
CLK
= 3GHz, f
D
= f
CLK
/2 input tran-
sition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (I
EE
)
vs. TEMPERATURE
MAX9381 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
18
20
22
24
16
-40 85
INPUTS AND
OUTPUTS OPEN
OUTPUT AMPLITUDE (V
OH
- V
OL
)
vs. CLK FREQUENCY
MAX9381 toc02
CLK FREQUENCY (GHz)
OUTPUT AMPLITUDE (mV)
2.52.01.51.00.503.0
400
500
600
700
800
300
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9381 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
603510-15-40 85
f
CLK
= 1.5GHz
FALL TIME
RISE TIME
117
119
121
123
125
115
MAX9381 toc04
TEMPERATURE (°C)
IN-TO-OUT PROPAGATION DELAY (ps)
330
340
350
360
320
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
603510-15-40 85
t
PHL
t
PLH
Detailed Description
The MAX9381 D flip-flop transfers the logic level at the
D input to the Q output on a rising edge transition of the
clock, provided the minimum setup and hold times are
met. By interchanging the CLK and CLK inputs, the flip-
flop functions as a falling-edge triggered flip-flop.
The input signals (D, D and CLK, CLK) are differential
and have a maximum differential input voltage of 3.0V
or V
CC
- V
EE
, whichever is less. To ensure that the out-
puts remain stable when the inputs are left open, each
of the inputs is driven low by a 75kΩ bias resistor con-
nected to V
EE
. If the D and D inputs are left open or at
V
EE
, the output is guaranteed to be a differential low on
the next low-to-high transition of the clock. If the CLK
and CLK inputs are left open or at V
EE
, the outputs
remain unchanged (Table 1). Terminate the outputs (Q,
Q) through 50Ω to V
CC
- 2V or an equivalent Thevenin
termination (see the Output Termination section).
ECL/PECL Operation
Output levels are referenced to V
CC
and are consid-
ered PECL or ECL, depending on the level of the V
CC
supply. With V
CC
connected to a positive supply and
V
EE
connected to GND, the outputs are PECL. The out-
puts are ECL when V
CC
is connected to GND and V
EE
is connected to a negative supply.
Applications Information
T Flip-Flop
The MAX9381 can be configured as a T flip-flop by
connecting Q to D and Q to D. This configuration pro-
vides an output at half the frequency of the clock. The
maximum operating frequency is determined by the
sum of the setup time, the propagation delay of the
MAX9381
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 D Noninverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
2 D Inverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
3 CLK Noninverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
4 CLK Inverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
5V
EE
Negative Supply
6 Q Inverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to V
CC
- 2V or equivalent.
7 Q Noninverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to V
CC
- 2V or equivalent.
8V
CC
Positive Supply. Bypass from V
CC
to V
EE
with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
D, D CLK, CLK Q, Q
L ↑ L
H ↑ H
Open or V
EE
↑ L
X Open or V
EE
No change
Table 1. Truth Table*
*Where logic states are differential, ↑ is a low-to-high transition
and X signifies a don’t care state.
V
CC
V
EE
V
IHD
(MAX)
(MIN)
(MIN)
V
ILD
(MAX)
INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION
V
IHD
V
ILD
V
ID
= 0
V
ID
= 0
V
ID
V
ID
V
OH
- V
OL
V
CC
V
OH
V
OL
V
EE
Figure 1. Input and Output Voltage Definitions
MAX9381
device and any added delay by circuit board traces.
The minimum supply voltage is 2.375V and is deter-
mined by input and output voltage range.
Output Termination
Terminate the outputs through 50Ω to V
CC
- 2V or use
equivalent Thevenin terminations. Terminate each Q and
Q outputs with identical termination on each for the lowest
output distortion. When a single-ended signal is taken
from the differential output, terminate both Q and Q.
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should be observed.
Power-Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors. Place the capac-
itors as close to the device as possible with the 0.01µF
capacitor closest to the device pins.
Use multiple vias when connecting the bypass capaci-
tors to ground. This reduces trace inductance, which
lowers power-supply bounce when drawing high tran-
sient currents.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners, or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 375
PROCESS: Bipolar
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
6 _______________________________________________________________________________________
D
D
CLK
CLK
Q
Q
t
S
t
H
t
PLH
Q - Q
t
R
20%
80%
0V (DIFFERENTIAL)
t
PHL
DIFFERENTIAL
OUTPUT
WAVEFORM
20%
80%
0V (DIFFERENTIAL)
t
F
Figure 2. CLK-to-Q Propagation Delay and Transition Timing Diagram
P1-P3P4-P6P7-P7

MAX9381ESA+T

Mfr. #:
Buy MAX9381ESA+T
Manufacturer:
Maxim Integrated
Description:
Flip Flops ECL/PECL Diff Data & Clock D Flip-Flop
Lifecycle:
New from this manufacturer.
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