XRT6164
4
Rev. 4.0.0
ELECTRICAL CHARACTERISTICS
Test Conditions: V
CC
= 5V +/- 5%, T
A
= 2C, Unless Otherwise Specified
Parameters Min. Typ. Max. Units Conditions
DC Electrical Characteristics
Supply Voltage 4.75 5 5.25 V
Analog Supply Current 48mA
Digital Supply Current 13 20 mA
Receiver
Input Signal 1 2.2 Vp Measured from Pins 1 or 16 with Respect to Pin 2
Dynamic Range 10 dB Maximum Cable Loss Range
Input Impedance 20 kΩ Measured Between Pins 1 and 16
Input Slicing Threshold 50 % Percent of Peak Input Signal Amplitude
Input Bias Voltage 1.45 V Measured at Pin 2
Loss of Signal Alarm Threshold 150 mVp Measured from Pins 1 or 16 with Respect to Pin 2
Loss of Signal Alarm Level +/-1.5 dB Difference Between Alarm-on and Alarm-off
Hysteresis Levels
Peak Detector Leakage -80 μA
Data Output Low 0.4 V Measured at Pins 5 or 12, I OUT = +1.6mA
Data Output High 3.6 V Measured at Pins 5 or 12, I OUT = -40μA
Alarm Output Low 0.4 V Measured at Pin 3; I OUT = +1.6mA
Alarm Output High V
CC
- V Measured at Pin 3; I OUT = -40μA
0.5
TCM Input Low Voltage 0.8 V Measured at Pin 15; I IN Min = -500μA, I IN Max =
+5μA
Transmitter
Input Low Voltage 0.8 V Measured at Pins 6, 11; I IN = -700μA
Input High Voltage 2.2 V Measured at Pins 6, 11; I IN = +5μA
Output Low Voltage 1 V Measured at Pins 8, 10; I OUT = -40mA
Output Low Current 40 mA Measured at Pins 8, 10; V OUT = 1V
Output Leakage Current -100 μA Measured at Pins 8, 10; V OUT = 10V Outputs in
off state
AC Electrical Characteristics
Receiver
Input Level 1 2.2 Vp Pin 1, 16 with Respect to Pin 2 1
Output Rise Time 50 ns Pins 5, 12; C L = 15pF, 10% to 90%
Output Fall Time 50 ns Pins 5, 12; C L =15pF, 90% to 10%
Notes:
1. Higher input voltages are possible if a resistive input attenuator is used.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
XRT6164
5
Rev. 4.0.0
ELECTRICAL CHARACTERISTIC (CONT’D)
Parameters Min. Typ. Max. Units Conditions
AC Electrical Characteristics (Cont’d)
Transmitter
Output Rise Time 50 ns Pins 8, 10; R L = 130, C L = 15pF, 10% to 90%
Output Fall Time 50 ns Pins 8, 10; R L = 130, C L = 15pF, 90% to 10%
Rising Edge Delay 100 ns Pins 8, 10; R L = 130, C L = 15pF, 50% to 50%
(I/P to O/P)
Falling Edge Delay 100 ns Pins 8, 10; R L = 130, C L = 15pF, 50% to 50%
(I/P to O/P)
Notes:
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 20V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature -65°C to +150°C . . . . . . .
. . . . .
Magnetic Supplier Information:
Pulse
Telecom Product Group
P.O. Box 12235
San Diego, CA 92112
Tel. (619) 674-8100
Fax. (619) 674-8262
Transpower Technologies, Inc.
24 Highway 28, Suite 202
Crystal Bay, NV 89402–0187
Tel. (702) 831–0140
Fax. (702) 831–3521
XRT6164
6
Rev. 4.0.0
SYSTEM DESCRIPTION
The XRT6164 is a general purpose line interface chip
that contains the receive and transmit circuitry neces-
sary to convert TTL logic levels to a bipolar signal both
to and from a twisted pair cable.
Receiver
The XRT6164 receiver section converts a balanced
bipolar signal that has been attenuated and distorted
by up to 10dB of twisted pair cable to active-low TTL
compatible logic levels.
The cable is transformer coupled to the receiver differ-
ential inputs (RX+IP, RX-IP) which are biased through
the input transformer secondary winding by a voltage
generated on-chip (I/P BIAS). The bipolar receive
signal is applied to a peak detector, and to a pair of data
comparators. The peak detector output voltage
charges an external capacitor connected to PEAK
CAP. This voltage generates a data comparator bias
level that is approximately 50% of the peak input pulse
amplitude. Thus, data slicing is automatically accom-
plished at the optimum level over the full cable loss
range. TTL compatible output stages buffer the re-
ceiver digital outputs (S+R, S-R) and provide active
low signals corresponding to received positive and
negative input pulses.
Loss of input signal is detected by a comparator that
monitors input signal level. An active-low TTL compat-
ible logic level (RX ALARM) indicates signal loss.
Comparator hysteresis prevents chatter on this output.
Ping-pong operation is made possible by the time
compression multiplex control input (TCM CON). A
logic 0 applied to this pin during transmission stores the
peak detector output voltage by disconnecting the
peak detector storage capacitor charge and discharge
paths. Since the receive data comparator bias voltage
is stored during transmit mode, it is immediately
available when receive mode resumes.
Transmitter
The XRT6164 transmitter section contains two
matched open collector output drivers that are capable
of driving the line transformer directly with a current up
to 40mA. The transmitter output drivers include diode
clamps to ensure non-saturating operation. Transmit-
ter digital inputs, which are active-high, are TTL com-
patible. External resistors are used between the trans-
mitter outputs and the output transformer primary to set
the output pulse amplitude.
APPLICATION INFORMATION
Figure 2 shows a general line driver application circuit
using the XRT6164. This device converts bipolar
transmit and receive signals in the 64Kbps to
1.544Mbps range to active-low TTL compatible logic
levels.
Bipolar signals that have been attenuated and dis-
torted by twisted pair cable are transformer-coupled to
the line side of the XRT6164 as shown on the left side
of Figure 2. Suggested transformers for both the input
and output applications are the Pulse types PE-65535
or TTI–7147 for 64Kbps use and the PE-65835 for
1.544Mbps applications.
The right side of Figure 2 shows the TTL compatible
digital inputs and outputs. Please refer to the pin
description section of this data sheet for detailed
information about each signal.

XRT6164CP-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs codirectionalIntrfc
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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