MAX8555/MAX8555A
Set the UVP Fault Threshold
Use a resistor-divider from the input supply to GND with
the center tap connected to UVP to set the undervoltage
threshold. Use a 10kΩ resistor from UVP to GND (R4 in
Figure 4) and calculate R3 as follows:
where V
UV
is the desired undervoltage trip point and
V
UVP
is the UVP reference threshold (0.4V typ). Connect
UVP to VL to disable the undervoltage-protection feature.
Set the OVP Fault Threshold
For a single-supply application, use a resistor-divider
from the output bus to GND with the center tap con-
nected to OVP to set the overvoltage threshold. Use a
10kΩ resistor from OVP to GND (R6 in Figure 4) and
calculate R5 as follows:
where V
OV
is the desired overvoltage threshold and V
OVP
is the OVP reference threshold (0.5V typ). Connect OVP
to GND to disable the overvoltage-protection feature.
For (n + 1) applications, the required circuit values are:
where the resistors are as shown in Figure 2.
MOSFET Selection
The MAX8555/MAX8555A drive N-channel MOSFETs.
The most important specification of the MOSFETs is
R
DS(ON)
. As load current flows through the external
MOSFET, V
DS
is generated from source to drain due to
the MOSFET’s on-resistance, R
DS(ON)
. The MAX8555/
MAX8555A monitor V
DS
of the MOSFETs at all times to
determine the state of the monitored power supply.
Selecting a MOSFET with a low R
DS(ON)
allows more
current to flow through the MOSFETs before the
MAX8555/MAX8555A detect reverse-current (I
REVERSE
)
and forward-current (I
FORWARD
) conditions.
Using Two MOSFETs
Two MOSFETs must be used for overvoltage protec-
tion. When using two external MOSFETs, the monitored
voltage equation becomes:
V
DSTOTAL
= R
DS(ON)1
x I
LOAD
+ R
DS(ON)2
x I
LOAD
Using One MOSFET
A single MOSFET can be used if the overvoltage-protec-
tion function is not needed. Connect CS+ to the source of
the MOSFET and CS- to the drain of the MOSFET.
Calculating GATE Current
The charge-pump output current is proportional to both
oscillator frequency and V
VL
. There is also a small inter-
nal load of approximately 6MΩ. The GATE current for a
given V
VL
and R
TIMER
is calculated as:
Layout Guidelines
It is important to keep all traces as short as possible
and to maximize the high-current trace dimensions to
reduce the effect of undesirable parasitic inductance.
The MOSFET dissipates a fair amount of heat due to
the high currents involved, especially during an over-
current condition. To dissipate the heat generated by
the MOSFET, make the power traces very wide with a
large amount of copper area and place the MAX8555
as close as possible to the drain of the external MOS-
FET. A more efficient way to achieve good power dissi-
pation on a surface-mount package is to lay out two
copper pads directly under the MOSFET package on
both sides of the board. Use enlarged copper mount-
ing pads on the top side of the board. Use a ground
plane to minimize impedance and inductance. In addi-
tion to the usual high-power considerations, here are
three tips to prevent false faults:
1) Kelvin connect CS+ and CS- to the external
MOSFET and route the two traces in parallel, as
close as possible, back to the IC.
2) Bypass V
DD
with a 0.01µF capacitor to ground and
bypass CS+ and CS- with a 1000pF capacitor to
ground.
3) Make the traces connected to UVP and OVP as
short as possible.
Refer to the MAX8555/MAX8555A evaluation kit for an
example of good PC board layout.
