© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 14
1 Publication Order Number:
MC100LVEP14/D
MC100LVEP14
2.5V / 3.3V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP14 is a low skew 1−to−5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
BB
output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50 W
even if only one output is being used. If an output pair is unused, both
outputs may be left open (unterminated) without affecting skew.
The common enable (EN
) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock; therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The MC100LVEP14, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVEP14 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Single−ended CLK input pin operation is limited to
a V
CC
≥ 3.0 V in PECL mode, or V
EE
≤ −3.0 V in NECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board.
Features
• 100 ps Device−to−Device Skew
• 25 ps Within Device Skew
• 400 ps Typical Propagation Delay
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
• NECL Mode:
V
CC
= 0 V with V
EE
= −2.375 V to −3.8 V
• LVDS Input Compatible
• Open Input Default State
• These Devices are Pb−Free and are RoHS Compliant
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
100
VP14
ALYWG
1
20
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
G
(Note: Microdot may be in either location)
