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IR1153SPBF

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IR1153S
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© 2011 International Rectifier
Lead Assignments & Definitions
IRS1144IRS1144
IR1144S
IRS1144IRS1144
IR1144S
IR1153
IR1153S
www.irf.com 8
© 2011 International Rectifier
IR1153 General Description
The μPFC IR1153 IC is intended for power factor
correction in continuous conduction mode Boost PFC
converters operating at fixed switching frequency with
average current mode control. The IC operates based
on IR's proprietary "One Cycle Control" (OCC) PFC
algorithm based on the concept of resettable
integrator.
Theory of Operation
The OCC algorithm based on the resettable integrator
concept works using two loops - a slow outer voltage
loop and a fast inner current loop. The outer voltage
loop monitors the VFB pin and generates an error
signal which controls the amplitude of the input current
admitted into the PFC converter. In this way, the outer
voltage loop maintains output voltage regulation. The
voltage loop bandwidth is kept low enough to not track
the 2xf
AC
ripple in the output voltage and thus
generates an almost DC error signal under steady
state conditions.
The inner current loop maintains the sinusoidal profile
of the input current and thus is responsible for power
factor correction. The information about the sinusoidal
variation in input voltage is inherently available in the
input line current (or boost inductor current). Thus
there is no need to sense the input voltage to
generate a current reference. The current loop
employs the boost inductor current information to
generate PWM signals with a proportional sinusoidal
variation. This controls the shape of the input current
to be proportional to and in phase with the input
voltage. Average current mode operation is envisaged
by filtering the switching frequency ripple from the
current sense signal using an appropriately sized on-
chip RC filter. This filter also contributes to the
bandwidth of the current control loop. Thus the filter
bandwidth has to be high enough to track the 120Hz
rectified, sinusoidal current waveform and also filter
out the switching frequency ripple in the inductor
current. In IR1153 this averaging function can
effectively filter high ripple current ratios (as high as
40% at maximum input current) to accommodate
designs with small boost inductances.
The IC determines the boost converter instantaneous
duty cycle based on the resettable integrator concept.
The required signals are the voltage feedback loop
error signal V
m
(which is the V
COMP
pin voltage minus a
DC offset of V
COMP,START
) and the current sense signal
V
ISNS
. The resettable integrator generates a cycle-by-
cycle, saw-tooth signal called the PWM Ramp which
has an amplitude V
m
and period 1/f
SW
hence a slope of
V
m*
f
SW
.
The current sense signal is amplified by the current
amplifier by a factor g
DC
and fed into the summing
node where it is subtracted from V
m
to generate the
summer voltage (= V
m
–g
DC
*V
ISNS
). The summer
voltage is compared with the PWM ramp by the
PWM comparator of the IC to determine the gate
drive duty cycle. The instantaneous duty is
mathematically given by:
D = (V
m
- g
DC
.V
ISNS
)/V
m
Assuming steady state condition where the voltage
feedback loop is well regulated (V
m
& V
OUT
are DC
signals) & hence instantaneous duty cycle follows
the boost-converter equation (D = 1 – V
IN
(t)/V
OUT
),
the control equation can be re-written as:
V
m
= g
DC
.V
ISNS
/(V
IN
(t)/V
OUT
)
Further, recognizing that V
ISNS
= I
L
(t).R
SNS
and re-
arranging yields:
g
DC
.I
L
(t).R
SNS
= V
m
V
IN
(t)/V
OUT
Since V
m
, V
OUT
& g
DC
are constant terms:
I
L
(t) α V
IN
(t)
Thus the inductor current follows the input voltage
waveform & by definition power factor correction is
achieved.
Feature set
Fixed Frequency Operation
The IC is programmed to operate at a fixed
frequency of 22.2kHz (Typ). Internalization of the
oscillator offers excellent noise immunity even in
the noisy PFC environment while integration of the
oscillator into the OCC core of the IC eliminates
need for digital calibration circuits. Both these
factors render the gate drive jitter free thus
contributing to elimination of audible noise in PFC
magnetics.
IC Supply Circuit & Low start-up current
The IR1153 UVLO circuit maintains the IC in UVLO
mode during start-up if VCC pin voltage is less than
the VCC turn-on threshold, V
CC,ON
and current
consumption is less than 75uA. Should VCC pin
voltage should drop below V
CC,UVLO
during normal
operation, the IC is pushed back into UVLO mode
and VCC pin has to exceed V
CC,ON
again for normal
operation. There is no internal voltage clamping of
the VCC pin.
User initiated Micropower Sleep mode
The IC can be actively pushed into a micropower
Sleep Mode where current consumption is less
than 75uA by pulling OVP/EN pin below the Sleep
threshold, V
SLEEP
even while VCC is above V
CC,ON
.
This allows the user to disable PFC during
application stand-by situations in order to meet
stand-by regulations. Since V
SLEEP
is less than 1V,
even logic level signals can be employed.
IR1153S
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© 2011 International Rectifier
IR1153 General Description
Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation components selected and is
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 750mA peak current drive
capability. The gate drive is internally clamped at
14.1V (Typ). Gate drive buffer circuits (especially
cost-effective base-followers) can be easily driven
with the GATE pin of the IC to suit any system
power level.
System Protection Features
IR1153 protection features include Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold V
BOP
, a
Brown-out situation is immediately detected the
following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters normal operation only after BOP pin
exceeds V
BOP(EN)
. During start-up the IC is held in
Stand-by Mode until this pin exceeds V
BOP(EN)
.
- OLP is activated whenever the VFB pin voltage
falls below V
OLP
threshold. Once open loop is
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
exceeds V
OLP
.
- The OVP pin is a dedicated pin for overvoltage
protection that safeguards the system even if
there is a break in the VFB feedback loop due to
resistor divider failure etc. An overvoltage fault is
triggered when OVP pin voltage exceeds the V
OVP
threshold of 106%VREF. The response of the IC
is to immediately terminate the gate drive output
and hold it in that state. The gate drive is re-
enabled only after OVP pin voltage drops below
V
OVP(RST)
threshold of 103% VREF. The exact
voltage level at which overvoltage protection is
triggered can be programmed by the user by
carefully designing the OVP pin resistor divider. It
is recommended NOT to set the OVP voltage
trigger limit less than 106% of DC bus voltage,
since this can endanger the situation where the
OVP reset limit will be less than the DC bus
voltage regulation point – in this condition the
voltage loop can become unstable.
- Soft-current limit is an output voltage fold-back
type protection feature encountered when the
PFC converter input current exceeds to a point
where the V
m
voltage saturates. As mentioned
earlier, the amplitude of input current is directly
proportional to V
m
, the error voltage of the
feedback loop. V
m
is clamped to a certain
maximum voltage inside the IC (given by
V
COMP,EFF
parameter in datasheet). If the input
current causes the V
m
voltage to saturate at its
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the V
OUT
voltage of the PFC
converter to fold-back. Since the highest current
is at the peak of the AC sinusoid, the droop in
duty cycle commences at the peak of the AC
sinusoid when the soft-current limit is
encountered. In most converters, the design of
the current sense resistor is performed based on
soft-current limit (i.e. V
m
saturation) and at the
system condition which demands highest input
current (minimum V
AC
& maximum P
OUT
).
- Cycle-by-cycle peak current limit protection
instantaneously turns-off the gate output
whenever the ISNS pin voltage exceeds V
ISNS(PK)
threshold in magnitude. The gate drive is held in
the low state as long as the overcurrent condition
persists. The gate drive is re-enabled when the
magnitude of ISNS pin voltage falls below the
V
ISNS(PK)
threshold. This protection feature
incorporates a leading edge blanking circuit to
improve noise immunity.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

IR1153SPBF

Mfr. #:
Buy IR1153SPBF
Manufacturer:
Infineon Technologies
Description:
Power Factor Correction - PFC Fixed 22.2kHz 750mA 20V 2mA 976mW
Lifecycle:
New from this manufacturer.
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