NBC12439, NBC12439A
http://onsemi.com
10
Table 11. Frequency Operating Range
VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:
Output Frequency (MHz) for
fXTAL = 16 MHz and for N =
M M[6:0] 10 12 14 16 18 20 B1 B2 B4 B8
20 0010100 400
21 0010101 420
22 0010110 440
23 0010111 414 460
24 0011000 432 480
25 0011001 400 450 500 400 200 100 50
26 0011010 416 468 520 416 208 104 52
27 0011011 432 486 540 432 216 108 54
28 0011100 448 504 560 448 224 112 56
29 0011101 406 464 522 580 464 232 116 58
30 0011110 420 480 540 600 480 240 120 60
31 0011111 434 496 558 620 496 248 124 62
32 0100000 448 512 576 640 512 256 128 64
33 0100001 462 528 594 660 528 264 132 66
34 0100010 408 476 544 612 680 544 272 136 68
35 0100011 420 490 560 630 700 560 280 140 70
36 0100100 432 504 576 648 720 576 288 144 72
37 0100101 444 518 592 666 740 592 296 148 74
38 0100110 456 532 608 684 760 608 304 152 76
39 0100111 468 546 624 702 780 624 312 156 78
40 0101000 400 480 560 640 720 800 640 320 160 80
41 0101001 410 492 574 656 738 656 328 164 82
42 0101010 420 504 588 672 756 672 336 168 84
43 0101011 430 516 602 688 774 688 344 172 86
44 0101100 440 528 616 704 792 704 352 176 88
45 0101101 450 540 630 720 720 360 180 90
46 0101110 460 552 644 736 736 368 184 92
47 0101111 470 564 658 752 752 376 188 94
48 0110000 480 576 672 768 768 384 192 96
49 0110001 490 588 686 784 784 392 196 98
50 0110010 500 600 700 800 800 400 200 100
51 0110011 510 612 714
52 0110100 520 624 728
53 0110101 530 636 742
54 0110110 540 648 756
55 0110111 550 660 770
56 0111000 560 672 784
57 0111001 570 684 798
58 0111010 580 696
59 0111011 590 708
60 0111100 600 720
61 0111101 610 732
62 0111110 620 744
63 0111111 630 756
64 1000000 640 768
65 1000001 650 780
66 1000010 660 792
67 1000011 670
68 1000100 680
69 1000101 690
70 1000110 700
71 1000111 710
72 1001000 720
73 1001001 730
74 1001010 740
75 1001011 750
76 1001100 760
77 1001101 770
78 1001110 780
79 1001111 790
80 1010000 800
NBC12439, NBC12439A
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11
Most of the signals available on the TEST output pin are
useful only for performance verification of the device itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the FOUT differential pair and the M
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clock tree. Figure 7 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the FOUT pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
T2 T1 T0 TEST OUTPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT B 4
Figure 5. Parallel Interface Timing Diagram
M[8:0]
N[1:0]
P_LOAD
VALID
t
h
t
s
M, N to P_LOAD
Figure 6. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
Last
Bit
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
T2 T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0
First
Bit
t
s
t
s
t
h
t
h
S_CLOCK to S_LOAD
S_DATA to S_CLOCK
Figure 7. Serial Test Clock Block Diagram
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK B N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
FDIV4
MCNT
LOW
F
OUT
MCNT
FREF
HIGH
TEST
MUX
7
0
TEST
F
OUT
(VIA ENABLE GATE)
N B
(1, 2, 4, 8)
0
1
PLL 12430
LATCH
Reset
PLOAD
M COUNTER
SLOAD
T0
T1
T2
VCO_CLK
SHIFT
REG
14BIT
DECODE
SDATA
SCLOCK
MCNT
FREF_EXT
NBC12439, NBC12439A
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12
APPLICATIONS INFORMATION
Using the OnBoard Crystal Oscillator
The NBC12439 and NBC12439A feature a fully
integrated onboard crystal oscillator to minimize system
implementation costs. The oscillator is a series resonant,
multivibrator type design as opposed to the more common
parallel resonant oscillator design. The series resonant
design provides better stability and eliminates the need for
large load capacitors. The oscillator is totally self contained
so that the only external component required is the crystal
per Figure 8 (do not use cyrstal load caps). As the oscillator
is somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the device as possible
to avoid any board level parasitics. To facilitate colocation,
surface mount crystals are recommended, but not required.
Because the series resonant design is affected by capacitive
loading on the crystal terminals, loading variation
introduced by crystals from different vendors could be a
potential issue. For crystals with a higher shunt capacitance,
it may be required to place a resistance, optional R
shunt
,
across the terminals to suppress the third harmonic.
Although typically not required, it is a good idea to layout
the PCB with the provision of adding this external resistor.
The resistor value will typically be between 500 W and
1 kW.
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the device with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified (a few hundred ppm
translates to kHz inaccuracy). Table 12 below specifies the
performance requirements of the crystals to be used with the
device.
Figure 8. Crystal Application
Table 12. Crystal Specifications
Parameter Value
Crystal Cut Fundamental AT Cut
Resonance Series Resonance*
Frequency Tolerance ±75 ppm at 25°C
Frequency/Temperature Stability ±150 ppm 0 to 70°C
Operating Range 0 to 70°C
Shunt Capacitance 57 pF
Equivalent Series Resistance (ESR)
50 to 80 W
Correlation Drive Level
100 mW
Aging 5 ppm/Yr
(First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
Power Supply Filtering
The NBC12439 and NBC12439A are mixed
analog/digital products and as such, exhibit some
sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The NBC12439 and NBC1239A provide
separate power supplies for the digital circuitry (V
CC
) and
the internal PLL (PLL_V
CC
) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phaselocked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V
CC
pin for the NBC12439 and
NBC12349A.
Figure 9 illustrates a typical power supply filter scheme.
The NBC12439 and NBC12439A are most susceptible to
noise with spectral content in the 1 KHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the
V
CC
supply and the PLL_V
CC
pin of the NBC12439 and
NBC12439A. From the data sheet, the PLL_V
CC
current
(the current sourced through the PLL_V
CC
pin) is typically
23 mA (28 mA maximum). Assuming that a minimum of
2.8 V must be maintained on the PLL_V
CC
pin, very little
DC voltage drop can be tolerated when a 3.3 V V
CC
supply
is used. The resistor shown in Figure 9 must have a
resistance of 1015 W to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor, it’s overall

NBC12439FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 3.3V/5V Programmable PLL Clock Generator
Lifecycle:
New from this manufacturer.
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