AD7854/AD7854L
REV. B
–11–
CALIBRATION REGISTERS
The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read
from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are
addressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
Table IV. Calibration Register Addressing
CALSLT1 CALSLT0 Comment
0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
1 0 This combination addresses the Offset Register. One register in total.
1 1 This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
When writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
When reading from the calibration registers a write to the con-
trol register is required to set the CALSLT0 and CALSLT1 bits
and also to set the RDSLT1 and RDSLT0 bits to 10 (this
addresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer points to the gain
calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register pointer
is automatically incremented after each full calibration register
write/read operation. The calibration register address pointer is
incremented after the high byte read or write operation in byte
mode. Therefore when reading from or writing to the calibra-
tion registers, the low byte transfer must be carried out first, i.e.,
HBEN is at logic zero. The order in which the 10 calibration
registers are arranged is shown in Figure 5. Read/Write opera-
tions may be aborted at any time before all the calibration
registers have been accessed, and the next control register write
operation resets the calibration register pointer. The flowchart
in Figure 6 shows the sequence for writing to the calibration
registers. Figure 7 shows the sequence for reading from the cali-
bration registers.
CALIBRATION REGISTERS
GAIN REGISTER
OFFSET REGISTER
DAC 1ST MSB REGISTER
(1)
(2)
(3)
DAC 8TH MSB REGISTER (10)
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 5. Calibration Register Arrangement
When reading from the calibration registers there are always two
leading zeros for each of the registers.
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
START
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
FINISHED
NO
YES
Figure 6. Flowchart for Writing to the Calibration Registers
