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SC621ULTRT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
SC621
16
PCB Layout Considerations
The layout diagram in Figure 1 illustrates a proper
two-layer PCB layout for the SC621 and supporting
components. Following fundamental layout rules is
critical for achieving the performance speci ed in the
Electrical Characteristics table. The following guidelines
are recommended when developing a PCB layout:
Place all bypass and decoupling capacitors —
C1, C2, CIN, COUT, CLDO1, CLDO2, and CBYP as
close to the device as possible.
All charge pump current passes through VIN,
VOUT, and the bucket capacitor connection
pins. Ensure that all connections to these pins
make use of wide traces so that the resistive
drop on each connection is minimized.
The thermal pad should be connected to the
ground plane using multiple vias to ensure
proper thermal connection for optimal heat
transfer.
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Applications Information (continued)
Make all ground connections to a solid
ground plane as shown in the example layout
(Figure 3).
If a ground layer is not feasible, the following
groupings should be connected:
PGND — CIN, COUT
AGND — Ground Pad, CLDO1, CLDO2,
CBYP
If no ground plane is available, PGND and
AGND should be routed back to the negative
battery terminal as separate signals using thick
traces. Joining the two ground returns at the
terminal prevents large pulsed return currents
from mixing with the low-noise return currents
of the LDOs.
Both LDO output traces should be made as
wide as possible to minimize resistive losses.
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COUT
C1 C2
CIN
CBYP
CLDO2
BL1
BL2
BL4
LDO1
LDO2
BYP
C1-
C2-
VIN
C1+
C2+
VOUT
SWIF
AGND
GREF
BL3
VIN
VOUT
SC621
FLEN
FL
GND
CLDO1
GND
PGND
NC
Figure 1 — Recommended PCB Layout
Figure 2 — Layer 1
Figure 3 — Layer 2
SC621
17
Register Map
Address D7 D6 D5 D4 D3 D2 D1 D0
Reset
Value
Description
0x00 FADE_1 FADE_0 FADE_EN BL_4 BL_3 BL_2 BL_1 BL_0 0x00
Backlight
Current
Control
0x01 0
(1)
0
(1)
0
(1)
0
(1)
BLEN_4 BLEN_3 BLEN_2 BLEN_1 0x00
Backlight
Enable Control
0x02 0
(1)
0
(1)
0
(1)
FLTO FL_2 FL_1 FL_0 FL/SPLB 0x10
Flash/Spotlight
Control
0x03 0
(1)
LDO2_2 LDO2_1 LDO2_0 LDO1_3 LDO1_2 LDO1_1 LDO1_0 0x00 LDO Control
Notes:
(1) 0 = always write a 0 to these bits
Register and Bit De nitions
Backlight Current Control Register (0x00)
This register is used to set the currents for the backlight
current sinks, as well as to enable and set the fade step
rate. These current sinks need to be enabled in the
Backlight Enable Control register to be active.
FADE[1:0]
These bits are used to set the rise/fall rate between two
backlight currents as follows:
FADE_1 FADE_0
Fade Feature
Rise/Fall Rate
(ms/step)
0 0 32
01 24
10 16
11 8
The number of steps in changing the backlight current will
be equal to the change in binary count of bits BL[4:0].
FADE_EN
This bit is used to enable or disable the fade feature. When
the fade function is enabled and a new backlight current
is set, the backlight current will change from its current
value to a new value set by bits BL[4:0] at a rate of 8ms to
32ms per step. A new backlight level cannot be written
during an ongoing fade operation, but an ongoing fade
operation may be cancelled by resetting the fade bit.
Clearing the fade bit during an ongoing fade operation
changes the backlight current immediately to the value
of BL[4:0]. The number of counts to complete a fade
operation equals the di erence between the old and new
backlight values to increment or decrement the BL[4:0]
bits. If the fade bit is cleared, the current level will change
immediately without the fade delay. The rate of fade may
be changed dynamically, even while a fade operation is
active, by writing new values to the FADE_1 and FADE_0
bits. The total fade time is determined by the number of
steps between old and new backlight values, multiplied
by the rate of fade in ms/step. The longest elapsed time
for a full scale fade-out of the backlight is nominally 1.024
seconds when the default interval of 32ms is used.
SC621
18
Register and Bit De nitions (continued)
BL[4:0]
These bits are used to set the current for the backlight
current sinks. All enabled backlight current sinks will sink
the same current, as shown in Table 1.
BL_4 BL_3 BL_2 BL_1 BL_0
Backlight Current
(mA)
00000 0.5
00001 1.0
00010 1.5
00011 2.0
00100 2.5
00101 3.0
00110 3.5
00111 4.0
01000 4.5
01001 5
01010 5.5
01011 6
01100 6.5
01101 7
01110 7.5
01111 8
10000 8.5
10001 9
10010 9.5
10011 10
10100 10.5
10101 11
10110 11.5
10111 12
11000 13
11001 14
11010 15
11011 17
11100 19
11101 21
11110 23
11111 25
Table 1 — Backlight Current Control Bits
BL Enable Control Register (0x01)
This register is used to enable the backlight current
sinks.
BLEN[4:1]
These bits are used to enable current sinks (active high,
default low).
BLEN_4 — Enable bit for backlight BL4
BLEN_3 — Enable bit for backlight BL3
BLEN_2 — Enable bit for backlight BL2
BLEN_1 — Enable bit for backlight BL1
When enabled, the current sinks will carry the current set
by the backlight current control bits BL[4:0], as shown in
Table 1.
Flash/Spotlight Control Register (0x02)
This register is used to con gure the ash time-out feature,
the  ash or spotlight current, and select  ash or spotlight
current ranges.
FLTO
This bit is used to enable the  ash safety time-out feature.
The default state is enabled with FLTO = 1. If this bit is set,
the device will turn o the ash after a nominal period of
1s. Two ways to re-enable the  ash function after a safety
time-out are:
Pull the FLEN pin low to re-enable the  ash
function
Clear and re-write FL[2:0]
FL[2:0]
These bits are used to set the current for the  ash current
sink when con gured for ash or spotlight by the FL/SPLB
bit. Bits FL[2:0] set the  ash or spotlight current, as shown
in Table 2.
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SC621ULTRT

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Buy SC621ULTRT
Manufacturer:
Semtech
Description:
LED Lighting Drivers CONSULT FCTRY FOR AVAILABILITY
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