LT8580
15
8580fa
For more information www.linear.com/LT8580
applicaTions inForMaTion
Driving SYNC high for an extended period of time effec-
tively stops the operating clock and prevents latch SR1
from becoming set (see the Block Diagram). As a result,
the switching operation of the LT8580 will stop.
The duty cycle of the SYNC signal must be between 35%
and 65% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
(1) SYNC may not toggle outside the frequency range of
200kHz
to 1.5MHz unless it is stopped low to enable
the free-running oscillator.
(2) The SYNC frequency can always be higher than the
free-running oscillator frequency, f
OSC
, but should not
be less than 25% below f
OSC
.
Operating Frequency Selection
There are several considerations in selecting the operat
-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz, and in
that case, a 1.5MHz switching converter frequency may be
employed. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade-off is efficiency, since the switching losses due
to NPN base charge (see Thermal Calculations), Schottky
diode charge, and other capacitive loss terms increase
proportionally with frequency.
Soft-Start
The LT8580 contains a soft-start circuit to limit peak switch
currents during start-up. High start-up current is inherent
in switching regulators in general since the feedback loop
is saturated due to V
OUT
being far from its final value. The
regulator tries to charge the output capacitor as quickly as
possible, which results in large peak currents.
The start-up current can be limited by connecting an
external capacitor (typically 100nF to 1µF) to the SS pin.
This capacitor is slowly charged to ~2.1V by an internal
280k resistor once the part is activated. SS pin voltages
below ~1.1V reduce the internal current limit. Thus, the
gradual ramping of the SS voltage also gradually increases
the current limit as the capacitor charges. This, in turn,
allows the output capacitor to charge gradually toward its
final value while limiting the start-up current.
In the event of a commanded shutdown or lockout (SHDN
pin), internal undervoltage lockout (UVLO) or a thermal
lockout, the soft-start capacitor is automatically discharged
to ~200mV before charging resumes, thus assuring that
the soft-start occurs after every reactivation of the chip.
Shutdown
The SHDN pin is used to enable or disable the chip. For
most applications, SHDN can be driven by a digital logic
source. Voltages above 1.4V enable normal active op
-
eration. Voltages below 300mV will shutdown the chip,
resulting in extremely low quiescent current.
While the
SHDN voltage transitions through the lockout
voltage range (
0.3V to 1.21V) the power switch is disabled
and the SR2 latch is set (see the Block Diagram). This
causes the soft-start capacitor to begin discharging, which
continues until the capacitor is discharged and active op
-
eration is enabled. Although the power switch is disabled,
SHDN voltages in the lockout range do not necessarily
reduce quiescent current until the
SHDN voltage is near
or below the shutdown threshold.
Also note that SHDN can be driven above V
IN
or V
OUT
as
long as the SHDN voltage is limited to less than 40V.
Figure 7. Chip States vs SHDN Voltage
(HYSTERESIS AND TOLERANCE)
SHUTDOWN
(LOW QUIESCENT CURRENT)
ACTIVE
(NORMAL OPERATION)
LOCKOUT
(POWER SWITCH OFF,
SS CAPACITOR DISCHARGED)
1.21V
0.0V
1.40V
0.3V
SHDN (V)
