LTC3802EUH#TRPBF Datasheet LTC3802EUH#PBF, LTC3802EGN#TRPBF, LTC3802EUH#TRPBF | P19-P21

LTC3802

3802f

To minimize the switching loss and reverse current flow at

light loads, the LTC3802 switches to a second mode of

operation: Burst Mode operation (Figure 5b). In Burst

Mode operation, at the end of the QB cycle, if the inductor

current approaches zero or goes negative, the LTC3802

turns off both drivers. The actual cutoff threshold is

proportional to the I

MAX

setting and is equal to:

––

IMAX

100

The –3mV built-in offset overcomes the random mis-

match in the burst compararator trip point and allows

Burst Mode operation at no load.

Once both MOSFETs shut off, the voltage at the SW pin will

float around V

OUT

, and the inductor current and the voltage

across the inductor will be close to zero. This prevents

current from flowing backwards in QB, eliminating that

power loss term.

The moment the LTC3802 enters Burst Mode operation,

both drivers skip a number of switching cycles until the

internal 36µs timeout forces the switcher to return to

continuous operation. This timeout eliminates the audible

noise from certain types of inductors when they are lightly

loaded. After the 36µs timeout, the LTC3802 forces one

continuous mode cycle and checks the inductor current at

the end of the period. If it is still too small, it enters Burst

Mode operation again. This pattern repeats until the out-

put is loaded. The LTC3802 returns to continuous mode

operation if it detects that CMPIN potential is 12mV below

or 15mV above its nominal bandgap voltage. Immediately

after returning to continuous mode operation, the regula-

tor output might continue to droop slightly until the feed-

back loop responds and requests an increase in duty cycle.

During sudden transient steps, the regulator output ripple

is limited by the feedback loop transient response and is

independent of the mode of operation.

The small 15mV and –12mV offset at the POS and NEG

RESET comparators ensure that after a transient load step,

the LTC3802 returns to continuous mode quickly. This

minimizes the output ripple under Burst Mode operation.

For proper Burst Mode operation, the LTC3802 requires

very precise CMPIN and FB sensing. To realize this,

CMPIN and FB must use the same resistive divider values

APPLICATIO S I FOR ATIO

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As the output load current decreases in continuous mode,

the average current in the inductor will reach a point where

it drops below half the ripple current. At this point, the

current in the inductor will reverse during a portion of the

switching cycle, or begin to flow from the output back to

the input. This does not adversely affect regulation, but

does cause additional losses as a portion of the inductor

current flows back and forth through the resistive power

switches, giving away a little more power each time and

lowering the efficiency. There are some benefits to allow-

ing this reverse current flow: the circuit will maintain

regulation even if the load current drops to zero and the

output ripple voltage and frequency remain constant at all

loads, easing filtering requirements. However, continuous

mode at low output current does cause losses in effi-

ciency. A portion of the inductor current flows back and

forth through the resistive power switches, causing I

losses. The drivers continue to switch QT and QB on and

off once a cycle. Each time an external MOSFET is turned

on, the internal driver must charge its gate to a potential

above the MOSFET’s source voltage; when the MOSFET is

turned off, that charge is lost to ground or SW. At the high

switching frequencies, the lost gate charges can add up to

tens of millicoulombs. As the load current continues to

drop, these charges quickly become the dominant power

loss term, reducing efficiency once again.

Figure 5a. Continuous Mode

Figure 5b. Burst Mode Operation

INDUCTOR CURRENT

RIPPLE

3802 F05a

AVERAGE

TIME

INDUCTOR CURRENT

RIPPLE

TIME

3802 F05b

AVERAGE

LTC3802

3802f

and all resistors should have better than 1% tolerance. If

this is not possible and Burst Mode operation is required,

the potential at CMPIN can be set slightly higher than FB

by using a slightly bigger resistor from CMPIN to ground.

This removes the requirement of having expensive resis-

tors at the FB and CMPIN pins, at the expense of having a

higher Burst Mode ripple and slightly different overvolt-

age and power good thresholds. To ensure clean Burst

Mode operation, the CMPIN and FB resistive divider re-

quires good layout technique. Both resistive dividers must

be connected to the same nodes and away from high

current paths.

Low load current efficiency depends strongly on proper

Burst Mode operation. In an ideal system, the gate drive is

the dominant loss term at low load currents. Burst Mode

operation turns off all output switching for several clock

cycles in a row, significantly cutting gate drive losses. As

the load current in Burst Mode operation falls toward zero,

the current drawn by the LTC3802 falls to a quiescent

level—about 6.5mA. To maximize low load efficiency,

make sure the LTC3802 is allowed to enter Burst Mode

operation as cleanly as possible.

Operating Frequency/Frequency Synchronization

The LTC3802 controller uses a constant frequency, phase-

lockable internal oscillator with its frequency determined

by an internal capacitor. This capacitor is charged by a

fixed current plus an additional current that is proportional

to the voltage applied to the PLLLPF pin. When the PLLIN

pin is not used, an internal pull-down current source

forces PLLIN to ground and the controller runs at a fixed

550kHz switching frequency.

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

phase-locked loop consists of an internal voltage con-

trolled oscillator, a divide by 12 frequency divider and a

phase detector. The voltage controlled oscillator monitors

the output of the phase detector at the PLLLPF pin. It

provides a linear relationship between the PLLLPF poten-

tial and the master oscillator frequency. A DC voltage input

from 0.5V to 1.9V corresponds to a 330kHz to 750kHz

master switching frequency.

The phase detector used is an edge sensitive digital circuit

which provides zero degree phase shift between the exter-

nal and internal oscillators. This type of phase detector will

not lock up on an input frequency close to the harmonics

of the VCO center frequency. The output of the phase

detector is a complementary pair of current sources

charging or discharging the external filter network on the

PLLLPF pin. A simplified block diagram is shown in

Figure␣ 6.

If the external frequency, f

PLLIN

, is greater than the oscil-

lator frequency, f

OSC

, current is sourced continuously,

pulling up the PLLLPF pin. When f

PLLIN

is less than f

OSC

current is sunk continuously, pulling down the PLLLPF

pin. If f

PLLIN

and f

OSC

are the same but exhibit a phase

difference, the current sources turn on for a period corre-

sponding to the phase difference. Thus the voltage on the

PLLLPF pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor, C

, holds the voltage. When

locked, the PLL aligns the turn off of the top MOSFET to the

falling edge of the synchronizing signal.

The loop filter components, C

and R

, smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components, C

and R

, determine how fast the loop

acquires lock. Typically R

= 10k and C

is between

0.01µF and 0.1µF.

The PHASMD pin determines the relative phases between

the TG1, TG2 and the PLLIN signals. When PHASEMD is

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Figure 6. Phase-Locked Loop Block Diagram

LTC3802

PLLLPF

3806 F06

VCO

INTERNAL MASTER CLOCK

÷12

PHASEMD

PLLIN

PHASE DETECTOR

LTC3802

3802f

floating, it sits at around 2V and the internal phase-locked

loop synchronizes TG1’s falling edge to the falling edge of

the PLLIN signal. When PHASEMD is high, these two

signals are 90° out of phase. TG1 and TG2 remains 180°

out of phase independent of PHASEMD input.

The PHASEMD signal together with the PLL circuit can be

used to synchronize an additional LTC3802 power supply

circuit to provide a 4-phase, 4-output solution. Compared

to an in-phase multiple controller solution, the LTC3802’s

4-phase design reduces the input capacitor ripple current

requirements and efficiency losses because the peak

current drawn from the input capacitor is spaced out

within the switching cycle.

EXTERNAL COMPONENTS SELECTION

and PV

Power Supplies

Power for the top and bottom MOSFET drivers is derived

from the PV

pin; the internal controller circuitry is de-

rived from the V

pin. Under typical operating conditions,

the total current consumption at these two pins should be

well below 100mA. Hence, PV

and V

can be connected

to an external auxiliary 5V power supply. If an auxiliary

supply is not available, a simple zener diode and a darlington

NPN buffer can be used to power up these two pins as

shown in Figure 7. To prevent switching noise from cou-

pling to the sensitive analog control circuitry, V

should

have a 10µF bypassed capacitor close to the device. The

BiCMOS process that allows the LTC3802 to include large

on-chip MOSFET drivers also limits the maximum PV

and V

voltage to 7V. This limits the practical maximum

auxiliary supply to a loosely regulated 7V rail. If V

drops

below 2.5V or PV

drops below V

by more than 1V, the

LTC3802 goes into undervoltage lockout and prevents the

power switches from turning on.

Top MOSFET Driver Supply

An external bootstrap capacitor, C

, connected to the

BOOST pin supplies the gate drive voltage for the topside

MOSFET. This capacitor is charged through diode DCP

from PV

when the switch node is low. When the top

MOSFET turns on, the switch node rises to V

and the

BOOST pin rises to approximately V

+ PV

. The boost

capacitor needs to store about 100 times the gate charge

required by the top MOSFET. In most applications a 0.1µF

to 1µF, X5R or X7R dielectric capacitor is adequate.

Power MOSFET Selection

The LTC3802 requires two external N-channel power

MOSFETs, one for the top (main) switch and one for the

bottom (synchronous) switch. Important parameters for

the power MOSFETs are the threshold voltage V

(GS)TH

breakdown voltage V

(BR)DSS

, maximum current I

DS(MAX)

on-resistance R

DS(ON)

and input capacitance.

The gate drive voltage is set by the 5V PV

supply.

Consequently, logic-level threshold MOSFETs must be

used in LTC3802 applications. If the PV

voltage is

expected to drop below 5V, then sub-logic level threshold

MOSFETs should be considered. Pay close attention to the

(BR)DSS

specification, because most logic-level MOSFETs

are limited to 30V or less. The MOSFETs selected should

have a V

(BR)DSS

rating greater than the maximum input

voltage and some margin should be added for transients

and spikes. The MOSFETs selected should also have an

DS(MAX)

rating of at least two times the maximum power

stage output current. Still, this may not be a sufficient

margin so it is advisable to calculate the MOSFET’s junc-

tion temperature to ensure that it is not exceeded.

The LTC3802 uses the bottom MOSFET as the current

sense element, particular attention must be paid to its

APPLICATIO S I FOR ATIO

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Figure 7. LTC3802 Power Supply Inputs

BOOST

PGND

INFF

0.1µF

DCP

OUT

5.6V

Q1: ZETEX FZT603

: MM5Z6V2ST1

LTC3802

SGND

3802 F07

10µF

10Ω

100Ω

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LTC3802EUH#TRPBF

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators 2-Phase, Dual, Step Dwn Synch Controller

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