10 DS608F1
CS5342
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, C
L
= 20 pF)
10. For a description of speed modes, please refer to Table 1 on page 14
11. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
Parameter Symbol Min Typ Max Unit
MCLK Specifications
MCLK Period t
clkw
26 - 30 ns
52 - 1302 ns
MCLK Pulse Duty Cycle 40 - 60 %
Master Mode
SCLK falling to LRCK t
mslr
-20 - 20 ns
SCLK falling to SDOUT valid t
sdo
--32ns
SCLK Duty Cycle Single-Speed
Double-Speed
Quad-Speed
-
-
-
50
50
33
-
-
-
%
%
%
Slave Mode
Single-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period t
sclkw
313 - - ns
SCLK Duty Cycle 45 - 55 %
SDOUT valid before SCLK rising t
stp
10 - - ns
SDOUT valid after SCLK rising t
hld
5--ns
SCLK falling to LRCK edge t
slrd
-20 - 20 ns
Double-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period (Note 11) t
sclkw
208 - - ns
SCLK Duty Cycle 45 - 55 %
SDOUT valid before SCLK rising t
stp
10 - - ns
SDOUT valid after SCLK rising t
hld
5--ns
SCLK falling to LRCK edge t
slrd
-20 - 20 ns
Quad-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period (Note 11) t
sclkw
104 - - ns
SCLK Duty Cycle 40 - 50 %
SDOUT valid before SCLK rising t
stp
10 - - ns
SDOUT valid after SCLK rising t
hld
5--ns
SCLK falling to LRCK edge t
slrd
-8 - 8 ns
