Philips Semiconductors Product specification
74F258A
Quad 2-line to 1-line selector/multiplexer, inverting
(3-State)
1996 Jan 05
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
TEST LIMITS
CONDITIONS
1
MIN TYP
2
MAX
V
OH
High-level output voltage V
CC
= MIN, V
IL
= MAX, ±10%V
CC
2.4 V
V
IH
= MIN, I
OL
= MAX ±5%V
CC
2.7 3.3 V
V
OL
Low-level output voltage V
CC
= MIN, V
IL
= MAX, ±10%V
CC
0.30 0.50 V
V
IH
= MIN, I
OL
= MAX ±5%V
CC
0.35 0.50 V
V
IK
Input clamp voltage V
CC
= MIN, I
I
= I
IK
–0.73 –1.2 V
I
I
Input current at maximum input voltage V
CC
= MAX, V
I
= 7.0V 100 µA
I
IH
High-level input current V
CC
= MAX, V
I
= 2.7V 20 µA
I
IL
Low-level input current V
CC
= MAX, V
I
= 0.5V –0.6 mA
I
OZH
Off-state output current, High-level voltage applied V
CC
= MAX, V
O
= 2.7V 50 µA
I
OZL
Off-state output current, High-level voltage applied V
CC
= MAX, V
O
= 0.5V –50 µA
I
OS
Short-circuit output current
3
V
CC
= MAX –60 –150 mA
I
CCH
I
1n
=4.5V, OE=I
0n
=S=GND 8.5 11.5 mA
I
CC
Supply current (total) I
CCL
V
CC
= MAX I
1n
=S=4.5V, OE=I
0n
=GND 17 23 mA
I
CCZ
I
1n
=OE=4.5V,I
0n
=S=GND 16 22 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of High-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C T
amb
= –55°C to +70°C
SYMBOL PARAMETER TEST CONDITIONS V
CC
= +5.0V V
CC
= +5.0V ± 10% UNIT
C
L
= 50pF, R
L
= 500Ω C
L
= 50pF, R
L
= 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
I
n
to Y
n
Waveform 1
3.0
1.0
4.5
2.5
6.0
4.0
2.5
1.0
7.0
4.5
ns
ns
t
PLH
t
PHL
Propagation delay
S to Y
n
Waveform 2
3.5
2.5
6.5
6.0
8.0
8.0
3.5
2.5
9.0
9.0
ns
ns
t
PZH
t
PZL
Output enable time
to High or Low level
Waveform 3
Waveform 4
4.0
4.0
6.0
5.5
7.5
7.5
3.5
3.5
8.5
8.5
ns
ns
t
PHZ
t
PLZ
Output disable time
from High or Low level
Waveform 3
Waveform 4
2.0
2.0
3.5
3.5
5.5
5.5
2.0
2.0
6.5
6.0
ns
ns
