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CY7C1061GN30-10ZSXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 10 of 18
Figure 7. Write Cycle No. 1 (CE Controlled)
[20, 21, 22]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW)
[20, 21, 22]
Switching Waveforms (continued)
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
t
Data I/O
Address
CE
WE
BHE, BLE
t
HD
t
SD
t
SCE
t
HA
t
AW
t
PWE
t
WC
t
BW
t
SA
t
LZWE
t
HZWE
Data I/O
Address
CE
WE
BHE,BLE
Notes
20. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
21. Data I/O is high impedance if OE
, BHE, and/or BLE = V
IH
.
22. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 11 of 18
Figure 9. Write Cycle No. 3 (BLE or BHE Controlled)
[23]
Switching Waveforms (continued)
t
HD
t
SD
t
BW
t
SA
t
HA
t
AW
t
PWE
t
WC
t
SCE
Data I/O
Address
BHE
,BLE
CE
WE
Note
23. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
CY7C1061GN30
Document Number: 001-93680 Rev. *A Page 12 of 18
Truth Table
CE
1
CE
2
OE WE BLE BHE I/O
0
–I/O
7
I/O
8
–I/O
15
Mode Power
H X X X X X High Z High Z Power down Standby (I
SB
)
X L X X X X High Z High Z Power down Standby (I
SB
)
L H L H L L Data out Data out Read all bits Active (I
CC
)
L H L H L H Data out High Z Read lower bits only Active (I
CC
)
L H L H H L High Z Data out Read upper bits only Active (I
CC
)
L H X L L L Data in Data in Write all bits Active (I
CC
)
L H X L L H Data in High Z Write lower bits only Active (I
CC
)
L H X L H L High Z Data in Write upper bits only Active (I
CC
)
L H H H X X High Z High Z Selected, outputs disabled Active (I
CC
)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY7C1061GN30-10ZSXI

Mfr. #:
Buy CY7C1061GN30-10ZSXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM Async SRAMS
Lifecycle:
New from this manufacturer.
Delivery:
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