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LTC1406CGN#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
4
LTC1406
TI I G CHARACTERISTICS
W
U
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SMPL(MAX)
Maximum Sampling Frequency ● 20 MHz
t
1
Clock Period (Notes 11, 12) ● 50 ns
t
2
Pulse Width High (Notes 11, 12) ● 25 ns
t
3
Pulse Width Low (Notes 11, 12) ● 25 ns
t
4
Output Delay C
L
= 15pF 15 25 ns
t
5
Pipeline Delay 5 Cycles
t
6
Aperture Delay 3ns
Aperture Jitter 5ps
RMS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V
DD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SMPL
= 20MHz and t
r
= t
f
= 2ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended A
IN
+
input with A
IN
–
tied to V
REF
= 2.5V.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CLK edge starts a conversion.
Note 12: At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times <25ns and performance may
be affected.
Note 13: V
IN
= –Full Scale.
Distortion vs Input Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
UW
INPUT FREQUENCY (Hz)
100k
S/(N + D) (dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M 10M 100M
1406 G01
S/(N + D) vs Input Frequency
INPUT FREQUENCY (Hz)
100k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
1M 10M 100M
1406 G03
THD
3RD HARMONIC
2ND HARMONIC
Signal-to-Noise Ratio vs
Input Frequency
INPUT FREQUENCY (Hz)
100k
SIGNAL-TO-NOISE RATIO (dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M 10M 100M
1406 G02
5
LTC1406
TYPICAL PERFORMANCE CHARACTERISTICS
UW
OUTPUT CODE
0
INL EOC ERROR (LSB)
256
1406 G07
64
128
192
1.0
0.5
0
–0.5
–1.0
32 96 160
224
Supply Current vs
Sampling Frequency
SAMPLING FREQUENCY (Hz)
100k
SUPPLY CURRENT (mA)
35
30
25
20
15
10
5
0
1M 10M
1406 G09
20M
INPUT FREQUENCY (Hz)
100k
SPURIOUS-FREE DYNAMIC RANGE (dB)
70
60
50
40
30
20
10
0
1M 10M 100M
1406 G04
Intermodulation Distortion Plot
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AMPLITUDE (dB)
1406 G05
0123
4
5
678910
f
SAMPLE
= 20MHz
f
IN1
= 3.500977MHz
f
IN2
= 3.598633MHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
DNL EOC ERROR (LSB)
256
1406 G06
64
128
192
1.0
0.5
0
–0.5
–1.0
32 96 160
224
INPUT FREQUENCY (Hz)
100k
COMMON MODE REJECTION (dB)
70
60
50
40
30
20
10
0
1M 10M 100M
1406 G08
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
Spurious-Free Dynamic Range
vs Input Frequency
PIN FUNCTIONS
UUU
OGND (Pin 1):
Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
V
BIAS
(Pin 4): Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10µF tantalum in par-
allel with 0.1µF or 10µF ceramic.
V
REF
(Pin 5): External 2.5V Reference Input.
Bypass to
analog ground plane with 10µF tantalum in parallel with
0.1µF or 10µF ceramic.
AGND (Pin 6): Analog Ground. Tie to analog ground plane.
A
IN
+
(Pin 7): ±1V Input. The maximum output code
occurs when [(A
IN
+
) – (A
IN
–
)] = 1V. The minimum output
code occurs when [(A
IN
+
) – (A
IN
–
)] = –1V.
A
IN
–
(Pin 8): ±1V Input. The maximum output code
occurs when [(A
IN
+
) – (A
IN
–
)] = 1V. The minimum output
code occurs when [(A
IN
+
) – (A
IN
–
)] = –1V. For single-
ended operation, tie A
IN
–
to a DC voltage (e.g., V
REF
).
6
LTC1406
PIN FUNCTIONS
UUU
AV
DD
(Pin 9): Analog 5V Positive Supply.
Bypass to ana-
log ground plane with 10µF tantalum in parallel with 0.1µF
or 10µF ceramic.
AGND (Pin 10): Analog Ground. Tie to analog ground plane.
DGND (Pin 11): Digital Ground for Internal Logic. Tie to
analog ground plane.
DV
DD
(Pin 12): Digital 5V Positive Supply.
Bypass to DGND
with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
NC (Pins 13, 14): No Internal Connection.
D7 to D0 (Pins 15 to 22): Digital Data Outputs. The out-
puts swing between OV
DD
and OGND.
OF/UF (Pin 23): Overflow/Underflow Bit. OF/UF high with
D7 to D0 all high indicates an overrange, OF/UF high with
D7 to D0 all low indicates an underrange condition. OF/UF
low indicates a conversion within the normal input range.
The outputs swing between OV
DD
and OGND.
CLK (Pin 24): Clock Input. Internal sample-and-hold tracks
the input signal when CLK is high and samples the input
signal on the falling edge.
AV
DD
= DV
DD
= V
DD
NOMINAL (V) ABSOLUTE MAXIMUM (V)
PIN NAME DESCRIPTION MIN TYP MAX MIN MAX
1 OGND Ground for Output Drivers 0 –0.3 V
DD
+ 0.3
2OV
DD
Supply for Output Drivers 2.7 3 or 5 5.25 –0.3 6
3 SHDN Shutdown Input, Active Low 0 V
DD
–0.3 10
4V
BIAS
Internal Bias Voltage 1.9 2.2 2.5 –0.3 V
DD
+ 0.3
5V
REF
External Reference Input 2 2.5 3 –0.3 V
DD
+ 0.3
6 AGND Analog Ground, Clean Ground 0 –0.3 V
DD
+ 0.3
7A
IN
+
Positive Analog Input, ±1V Span 0 V
DD
–0.3 V
DD
+ 0.3
8A
IN
–
Negative Analog Input 0 V
DD
–0.3 V
DD
+ 0.3
9AV
DD
Analog Supply 4.75 5 5.25 –0.3 6
10 AGND Analog Ground, Substrate Ground 0 –0.3 V
DD
+ 0.3
11 DGND Digital Ground 0 –0.3 V
DD
+ 0.3
12 DV
DD
Digital Supply 4.75 5 5.25 –0.3 6
13 to 14 NC No Connect, No Internal Connection
15 to 22 D7 to D0 Data Outputs OGND OV
DD
–0.3 V
DD
+ 0.3
23 OF/UF Overflow/Underflow Output OGND OV
DD
–0.3 V
DD
+ 0.3
24 CLK Clock Input 0 V
DD
–0.3 10
TI I G DIAGRA
UW W
ANALOG
SIGNAL
CLOCK
N – 1
N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
1406 TD
N
t
6
N + 1
DATA OUT
t
3
t
1
t
2
N + 2
N + 3
N + 4
N + 6
N + 5
t
4
t
5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC1406CGN#TRPBF

Mfr. #:
Buy LTC1406CGN#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC L Pwr, 8-B, 20Msps, Smpl A/D Conv
Lifecycle:
New from this manufacturer.
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