74ABT16374BDL,118 Datasheet 74ABT16374BB,518, 74ABT16374BB,557, 74ABT16374BDGG,518 | P4-P6

Philips Semiconductors Product data

74ABT16374B

16-bit D-type flip-flop; positive-edge trigger

(3-State)

2004 Mar 08

4

LOGIC SYMBOL

32

1Q0 1Q1 1Q2

65

1Q3

47 46 44 43

1D0 1D1 1D2 1D3

48

1

98

1Q4 1Q5 1Q6

1211

1Q7

41 40 38 37

1D4 1D5 1D6 1D7

1CP

1OE

1413 1716

36 35 33 32

25

24

2019 2322

30 29 27 26

2Q0 2Q1 2Q2 2Q3

2D0 2D21 2D2 2D3

2Q4 2Q5 2Q6 2Q7

2D4 2D5 2D6 2D7

2CP

2OE

SH00078

LOGIC SYMBOL (IEEE/IEC)

1EN

1 ∇

C1

2EN

C2

1D

2 ∇

2D

SH00077

1

48

24

25

47

46

44

43

41

40

38

37

36

35

33

32

30

29

2

3

5

6

8

9

11

12

13

14

16

17

19

20

22

2326

27

1OE

1CP

2OE

2CP

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

LOGIC DIAGRAM

CP Q

D

nD0

nQ0

CP Q

D

nD1

CP Q

D

nD2

CP Q

D

nD3

CP Q

D

nD4

CP Q

D

nD5

CP Q

D

nD6

CP Q

D

nD7

nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7

nCP

nOE

SA00327

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

OPERATING MODE

nOE nCP nDx

REGISTER

nQ0 – nQ7

OPERATING

MODE

L

↑

l

h

L

H

L

H

Load and read register

L ↑ X NC NC Hold

H

↑

X

nDx

NC

nDx

Z

Disable outputs

H = HIGH voltage level

h = HiIGH voltage level one set-up time prior to the HIGH-to-LOW E transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW E transition

NC= No change

X = Don’t care

Z = High-impedance “off” state

↑ = LOW-to-HIGH clock transition

↑

= Not a LOW-to-HIGH clock transition

Philips Semiconductors Product data

74ABT16374B

16-bit D-type flip-flop; positive-edge trigger

(3-State)

2004 Mar 08

5

ABSOLUTE MAXIMUM RATINGS

1,

2

SYMBOL

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +7.0 V

I

IK

DC input diode current V

I

< 0 V –18 mA

V

I

DC input voltage

3

–1.2 to +7.0 V

I

OK

DC output diode current V

O

< 0 V –50 mA

V

OUT

DC output voltage

3

output in Off or HIGH state –0.5 to +5.5 V

I

O

DC out

p

ut current

output in LOW state 128 mA

I

OUT

DC

o

u

tp

u

t

c

u

rrent

output in HIGH state –64 mA

T

stg

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN MAX

UNIT

V

CC

DC supply voltage 4.5 5.5 V

V

I

Input voltage 0 V

CC

V

IH

HIGH-level input voltage 2.0 – V

V

IL

LOW-level Input voltage – 0.8 V

I

OH

HIGH-level output current – –32 mA

I

OL

LOW-level output current – 64 mA

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

Operating free-air temperature range –40 +85 °C

Philips Semiconductors Product data

74ABT16374B

16-bit D-type flip-flop; positive-edge trigger

(3-State)

2004 Mar 08

6

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS T

amb

= +25 °C

T

amb

= –40 °C

to +85 °C

UNIT

MIN TYP MAX MIN MAX

V

IK

Input clamp voltage V

CC

= 4.5 V; I

IK

= –18 mA – –0.9 –1.2 – –1.2 V

V

CC

= 4.5 V; I

OH

= –3 mA; V

I

= V

IL

or V

IH

2.5 2.9 – 2.5 – V

V

OH

HIGH-level output voltage V

CC

= 5.0 V; I

OH

= –3 mA; V

I

= V

IL

or V

IH

3.0 3.4 – 3.0 – V

V

CC

= 4.5 V; I

OH

= –32 mA; V

I

= V

IL

or V

IH

2.0 2.4 – 2.0 – V

V

OL

LOW-level output voltage V

CC

= 4.5 V; I

OL

= 64 mA; V

I

= V

IL

or V

IH

– 0.42 0.55 – 0.55 V

V

RST

Power-up output voltage

3

V

CC

= 5.5 V; I

O

= 1 mA; V

I

= GND or V

CC

– 0.13 0.55 – 0.55 V

I

Input leakage current V

CC

= 5.5 V; V

I

= V

CC

or GND – 0.01 ±1 – ±1 µA

I

OFF

Power-off leakage current V

CC

= 0.0 V; V

O

or V

I

≤ 4.5 V – ±5.0 ±100 – ±100 µA

I

PU/PD

Power-up/down 3-State

output current

4

V

CC

= 2.1 V; V

O

= 0.5 V;

V

I

= GND or V

CC

; V

OE

= GND

– ±5.0 ±50 – ±50 µA

I

OZH

3-State output HIGH current V

CC

= 5.5 V; V

O

= 2.7 V; V

I

= V

IL

or V

IH

– 0.5 10 – 10 µA

I

OZL

3-State output LOW current V

CC

= 5.5 V; V

O

= 0.5 V; V

I

= V

IL

or V

IH

– –0.5 –10 – –10 µA

I

CEX

Output HIGH leakage

current

V

CC

= 5.5 V; V

O

= 5.5 V; V

I

= GND or V

CC

– 5.0 50 – 50 µA

I

O

Output current

1

V

CC

= 5.5 V; V

O

= 2.5 V –50 –70 –180 –50 –180 mA

I

CCH

V

CC

= 5.5 V; Outputs HIGH;

V

I

= GND or V

CC

– 0.5 2 – 2 mA

I

CCL

Quiescent supply current

V

CC

= 5.5 V; Outputs LOW;

V

I

= GND or V

CC

– 8 19 – 19 mA

I

CCZ

V

CC

= 5.5 V; Outputs 3-State;

V

I

= GND or V

CC

– 0.5 2 – 2 mA

∆I

CC

Additional supply current

per input pin

2

V

CC

= 5.5 V; one input at 3.4 V,

other inputs at V

CC

or GND

– 5 100 – 100 µA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4 V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V

CC

between 0 V and 2.1 V with a transition time of up to 10 msec. From V

CC

= 2.1 V to V

CC

= 5 V ± 10% a

transition time of up to 100 µsec is permitted.

5. Unused pins at V

CC

or GND.

AC CHARACTERISTICS

GND = 0 V, t

R

= t

F

= 2.5 ns, C

L

= 50 pF, R

L

= 500 Ω

LIMITS

SYMBOL PARAMETER WAVEFORM

T

amb

= +25 °C

V

CC

= +5.0 V

T

amb

= –40 to +85 °C

V

CC

= +5.0V ± 0.5 V

UNIT

MIN TYP MAX MIN MAX

f

MAX

Maximum clock frequency 1 180 260 – – – MHz

t

PLH

t

PHL

Propagation delay

nCP to nQx

1

1.7

1.4

2.6

2.2

4.0

3.4

1.7

1.4

4.7

3.9

ns

t

PZH

t

PZL

Output enable time

to HIGH and LOW level

3

4

1.3

2.4

2.3

3.7

3.4

1.3

4.7

4.6

ns

t

PHZ

t

PLZ

Output disable time

from HIGH and LOW level

3

4

1.9

1.7

3.1

2.6

4.6

4.0

1.9

1.7

5.5

4.4

ns

74ABT16374BDL,118

74ABT16374BDL,118

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