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DS1314S-2

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DS1314
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NOTES:
2. All voltages referenced to ground.
3. Measured with outputs open circuited.
4. I
CCO1
is the maximum average load which the DS1314 can supply to attached memories at V
CCO
≥
V
CCI
-0.2V.
5. I
CCO1
is the maximum average load which the DS1314 can supply to attached memories at V
CCO
≥
V
CCI
-0.3V.
6. All inputs within 0.3V of ground or V
CCI
.
7. I
CCO2
is the maximum average load current which the DS1314 can supply to the memories in the
battery-backup mode.
8. Measured with a load as shown in Figure 2.
9. Chip Enable Output (
CEO
) can only sustain leakage current in the battery-backup mode.
10.
CEO
will be held high for a time equal to t
REC
after V
CCI
crosses V
CCTP
on power-up.
11.
BW
and
RST
are open drain outputs and as such cannot source current. External pull-up resistors
should be connected to these pins for proper operation. Both
BW
and
RST
can sink 10 mA.
12. t
CE
maximum must be met to ensure data integrity on power-down.
13. In battery-backup mode, inputs must never be below ground or above V
CCO
.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: See below
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
OUTPUT LOAD Figure 2
* INCLUDING SCOPE AND JIG CAPACITANCE
DS1314
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ORDERING INFORMATION
PART
TEMP
RANGE
PIN-PACKAGE
DS1314+
-40°C to +85°C
8 PDIP
DS1314S-2+
-40°C to +85°C
8 SO
DS1314S+
-40°C to +85°C
16 SO
DS1314E+
-40°C to +85°C
20 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 PDIP
P8+2
21-0043
8 SO
S8+4
21-0041
90-0096
16 SO
W16+1
21-0042
90-0107
20 TSSOP
U20+1
21-0066
90-0116
DS1314
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601- 1000
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1314 data
sheet. Please review this summary carefully.
1. Changed V
BAT
max to 6V.
2. Changed V
CCTP
values to 2.8 - 3.0V (TOL = GND) and 2.5 - 2.7V (TOL = V
CC
).
3. Changed t
BABW
from 7s to 1s max.
4. Changed block diagram to show U L compliance.
The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1314 data
sheet. Please review this summary carefully.
1. Changed AC test conditions.
2. Changed t
PD
to 20 max & 12 typ.
The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1314 data
sheet. Please review this summary carefully.
1. Changed V
CCI
mins from 3.05V to 3.0V (TOL=GND) and from 275V to 2.7V (TOL=V
CCD
) (this
should have been done on 06/12/97 revision but was overlooked).
2. Specified Input Capacitance as being only for
CEI
, TOL and Output Capacitance as being only for
CEO
,
BW
and
RST
. This is not a change but rather clarification.
3. Removed “preliminary” from title bar.
The following represent the key differences between 12/16/97 and 6/12 version of the DS1314 data sheet.
Please review this summary carefully.
1. Update soldering, ordering, package information, and notes.
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DS1314S-2

Mfr. #:
Buy DS1314S-2
Manufacturer:
Description:
IC CTRLR NV W/BATT MON 3V 8-SOIC
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