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CY24713KSXCT

P1-P3P4-P5
CY24713
Set-top Box Clock Generator with VCXO
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-07396 Rev. *B Revised March 26, 2010
Features
■
Integrated phase-locked loop (PLL)
■
Low-jitter, high-accuracy outputs
■
VCXO with analog adjust
■
3.3V Operation
■
8-pin SOIC
Benefits
■
High-performance PLL tailored for Set Top Box applications
■
Meets critical timing requirements in complex system designs
■
Large ±150-ppm range, better linearity
■
Meet industry standard voltage platforms
■
Industry standard packaging saves on board space
Pin Configuration
Figure 1. CY24713, 8-Pin SOIC
Part Number Outputs Input Frequency Range Output Frequencies
CY24713 3 27-MHz pullable crystal input
per Cypress specification
4.9152 MHz, 13.5 MHz, 27 MHz
Logic Block Diagram
Table 1. Pin Definition
Name Number Description
XIN 1 Reference Crystal Input
VDD 2 3.3V Voltage Supply
VCXO 3 Input Analog Control for VCXO
VSS 4 Ground
CLK_B 5 13.5-MHz Clock Output
CLK_A 6 4.9152-MHz Clock Output
CLK_C 7 27-MHz Clock Output
XOUT
[1]
8 Reference Crystal Output
Note
1. Float X
OUT
if X
IN
is externally driven.
[+] Feedback
CY24713
Document #: 38-07396 Rev. *B Page 2 of 5
Absolute Maximum Conditions
Parameter Description Min Max Unit
V
DD
Supply Voltage –0.5 7.0 V
T
S
Storage Temperature
[2]
–65 125 °C
T
J
Junction Temperature – 125 °C
Digital Inputs V
SS
– 0.3 V
DD
+ 0.3 V
Digital Outputs referred to V
DD
V
SS
– 0.3 V
DD
+ 0.3 V
Electrostatic Discharge – 2000 V
Analog Input –0.5 7.0 V
Pullable Crystal Specifications
Parameter Description Condition Min Typ. Max Unit
F
NOM
Nominal crystal frequency Parallel resonance, funda-
mental mode, AT cut
–27–MHz
C
LNOM
Nominal load capacitance – 14 – pF
R
1
Equivalent series resistance (ESR) Fundamental mode – – 25 Ω
R
3
/R
1
Ratio of third overtone mode ESR to fundamen-
tal mode ESR
Ratio used because typical R
1
values are much less than the
maximum spec.
3––
DL Crystal drive level No external series resistor as-
sumed
–0.52.0mW
F
3SEPHI
Third overtone separation from 3*F
NOM
High side 300 – – ppm
F
3SEPLO
Third overtone separation from 3*F
NOM
Low side – – –150 ppm
C
0
Crystal shunt capacitance – – 7 pF
C
0
/C
1
Ratio of shunt to motional capacitance 180 – 250
C
1
Crystal motional capacitance 14.4 18 21.6 pF
Note
2. Rated for 10 years
Recommended Operating Conditions
Parameter Description Min Typ. Max Unit
V
DD
Operating Voltage 3.135 3.3 3.465 V
T
A
Ambient Temperature 0 – 70 °C
C
LOAD
Max. Load Capacitance – – 15 pF
t
PU
Power up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
0.05 – 500 ms
DC Electrical Characteristics
Parameter Description Conditions Min Typ. Max Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
= 3.3V 12 24 – mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
= 3.3V 12 24 – mA
C
IN
Input Capacitance – – 7 pF
I
IZ
Input Leakage Current – 5 – μA
f
ΔXO
VCXO pullability range ±150 – – ppm
V
VCXO
VCXO input range 0 – V
DD
V
I
VDD
Supply Current – 25 30 mA
[+] Feedback
CY24713
Document #: 38-07396 Rev. *B Page 3 of 5
AC Electrical Characteristics
(V
DD
= 3.3V)
Parameter
[3]
Description Conditions Min Typ. Max Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of V
DD
45 50 55 %
ER
0
Rising Edge Rate Output Clock Edge Rate, Measured from 20% to
80% of
V
DD,
C
LOAD
= 15 pF Figure 4.
0.8 1.4 – V/ns
EF
1
Falling Edge Rate Output Clock Edge Rate, Measured from 80% to
20% of
V
DD,
C
LOAD
= 15 pF Figure 4.
0.8 1.4 – V/ns
t
9
Clock Jitter Peak-Peak period jitter maximum absolute jitter – 200 250 ps
t
10
PLL Lock Time – – 3 ms
Figure 2. Test Circuit
0.1 μF
V
DD
CLK out
C
LOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
Figure 3. Duty Cycle Definition; DC = t2/t1
Note
3. Not 100% tested
[+] Feedback
P1-P3P4-P5

CY24713KSXCT

Mfr. #:
Buy CY24713KSXCT
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN SET-TOP 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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