Evaluates: MAX1011
MAX1011 Evaluation Kit
6 _______________________________________________________________________________________
Digital Outputs
The TTL/CMOS-compatible digital outputs are present-
ed in parallel at connector J1. The data format is offset
binary with the MSB as D5 and the LSB as D0. The row
of pins closest to the board edge is digital output
ground (OGND), while the data bits occupy the inside
row. Located at the end of the connector is the pin for
the output clock labeled DCLK. This signal can be
used to latch the parallel-output data for capture into a
logic analyzer or external DSP circuitry. The digital out-
put is updated on DCLK’s rising edge (see the timing
diagram in the MAX1011 data sheet).
_____________Layout Considerations
The MAX1011 EV kit layout has been optimized for
high-speed signals. Careful attention has been given to
grounding, power-supply bypassing, and signal-path
layout to minimize coupling between the analog and
digital sections of the circuit. For example, the ground
plane has been removed under the tank circuitry to
reduce stray-capacitive loading on the relatively small
capacitors required in the resonant tank formed by C6,
L1, and D1. Other layout considerations are detailed in
the following sections.
Power Supplies and Grounding
The EV kit features separate analog and digital power
supplies and grounds for best dynamic performance. A
thin trace located on the backside of the circuit board
near the VCC power-supply connector ties the analog
and output ground planes together. This trace can be
cut if the power-supply grounds are referenced else-
where.
Referencing analog and digital grounds together at a
single point usually avoids ground loops and corruption
of sensitive analog circuitry by noise from the digital
outputs. If the ground trace on the backside of the
board is cut, observe the absolute maximum ratings
between the two grounds.
Bypassing
Proper bypassing is essential to achieve the best
dynamic performance from the converter. The
MAX1011 EV kit uses 10µF bypass capacitors located
close to the power-supply connectors on the board to
filter low-frequency supply ripple. High-frequency
bypassing is accomplished with ceramic-chip capaci-
tors located very close to the device’s supply pins.
As the digital outputs toggle, transient currents in the
V
CCO
supply can couple into sensitive analog circuitry
and severely degrade the converter’s effective number
of bits performance. Of particular concern is effectively
bypassing V
CCO
to OGND. For best results, locate the
bypass capacitor on the same side of the board and
place it close to the device. This avoids the use of
through-holes and results in lower series inductance.
The capacitor size chosen for the EV kit (size 0603)
keeps the layout compact. Finally, the modest value
(47pF) and small size result in a high self-resonant fre-
quency for effective high-frequency bypassing.
__________Applications Information
To achieve the full dynamic potential from the convert-
er, minimize the capacitive loading on the digital out-
puts to reduce the transient currents at V
CCO
and
OGND. The maximum capacitance per output bit
should be less than 15pF. For example, the capaci-
tance of the digital-output traces and the J1 connector
on the EV kit is about 1.5pF per trace. In an applica-
tions circuit, this could be further reduced by locating
the digital receiving chip very close to the MAX1011
and removing the ground plane from under the output
bit traces.
A logic analyzer can be connected to the J1 connector
on the EV kit for evaluation purposes. The analyzer
should be directly connected to the EV kit without any
additional ribbon cables. Even a short length of ribbon
cable can exceed the maximum recommended capaci-
tive loading of the digital outputs. A typical high-speed
logic-analyzer probe adds about another 8pF loading
per digital bit, which is acceptable for good dynamic
performance.
