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HEF4011BT-Q100J

P1-P3P4-P6P7-P9P10-P12
HEF4011B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 3 of 11
NXP Semiconductors HEF4011B-Q100
Quad 2-input NAND gate
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
[1] For SO14 packages: above T
amb
= 70 C, P
tot
derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 3. Function table
[1]
Input Output
nA nB nY
LLH
LHH
HLH
HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current - 10 mA
I
DD
supply current - 50 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +125 C
P
tot
total power dissipation T
amb
= 40 C to + 125 C
[1]
-500mW
P power dissipation per output - 100 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3 - 15 V
V
I
input voltage 0 - V
DD
V
T
amb
ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate V
DD
= 5 V --3.75s/V
V
DD
= 10 V --0.5s/V
V
DD
= 15 V --0.08s/V
HEF4011B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 4 of 11
NXP Semiconductors HEF4011B-Q100
Quad 2-input NAND gate
9. Static characteristics
Table 6. Static characteristics
V
SS
= 0 V; V
I
=V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= +25 C T
amb
= +85 C T
amb
= +125 C Unit
Min Max Min Max Min Max Min Max
V
IH
HIGH-level
input voltage
I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V7.0-7.0-7.0- 7.0 -V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level
input voltage
I
O
< 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
V
OH
HIGH-level
output voltage
I
O
< 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level
output voltage
I
O
< 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
I
OH
HIGH-level
output current
V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
V
O
= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
V
O
= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
V
O
= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
I
OL
LOW-level
output current
V
O
= 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
V
O
= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
V
O
= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
I
I
input leakage
current
15 V - 0.1 - 0.1 - 1.0 - 1.0 A
I
DD
supply current all valid input
combinations;
I
O
=0A
5 V - 0.25 - 0.25 - 7.5 - 7.5 A
10 V - 0.5 - 0.5 - 15.0 - 15.0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 A
C
I
input
capacitance
---7.5-- - -pF
HEF4011B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 5 of 11
NXP Semiconductors HEF4011B-Q100
Quad 2-input NAND gate
10. Dynamic characteristics
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
L
in pF).
[2] t
pd
is the same as t
PLH
and t
PHL
.
Table 7. Dynamic characteristics
T
amb
= 25
C; for waveforms see Figure 4; for test circuit, see Figure 5; unless otherwise specified.
Symbol Parameter Extrapolation formula
[1]
V
DD
Min Typ Max Unit
t
pd
propagation delay 28 + 0.55 C
L
5 V
[2]
- 55 110 ns
14 + 0.23 C
L
10 V - 25 45 ns
12 + 0.16 C
L
15 V - 20 35 ns
t
THL
HIGH to LOW output transition time 10 + 1.00 C
L
5 V - 60 120 ns
9 + 0.42 C
L
10 V - 30 60 ns
6 + 0.28 C
L
15 V - 20 40 ns
t
TLH
LOW to HIGH output transition time 10 + 1.00 C
L
5 V - 60 120 ns
9 + 0.42 C
L
10 V - 30 60 ns
6 + 0.28 C
L
15 V - 20 40 ns
Table 8. Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula Where
P
D
dynamic power dissipation 5 V P
D
= 1300 f
i
+ (f
o
C
L
) V
DD
2
(W) f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
(f
o
C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
10 V P
D
= 6000 f
i
+ (f
o
C
L
) V
DD
2
(W)
15 V P
D
= 20100 f
i
+ (f
o
C
L
) V
DD
2
(W)
P1-P3P4-P6P7-P9P10-P12

HEF4011BT-Q100J

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Manufacturer:
Nexperia
Description:
Logic Gates HEF4011BT-Q100/SO14/REEL 13" Q
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