
DocID026047 Rev 2 3/22
SR2 Description
22
1 Description
The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset
push-button closures do not cause system resets. This is done by implementing extended
Smart Reset™ input delay time (t
SRC
) and combined push-button inputs, which together
ensures a safe reset and eliminates the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish
between a software generated interrupt and a hard system reset. When the input push-
button are connected to microcontroller interrupt inputs, and are closed for a short time, the
processor can only be interrupted. If the system still does not respond properly, continuing
to keep the push-button closed for the extended setup time t
SRC
causes a hard reset of the
processor through the reset output.
The SR2 has two combined delayed Smart Reset™ inputs (SR0
, SR1) with preset delayed
Smart Reset™ setup time (t
SRC
). The reset output is asserted after both of the Smart
Reset™ inputs were held active for the selected t
SRC
delay time. Depending on selected
option the RST
output remains asserted either until at least one SR input goes to inactive
logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse
duration is fixed for t
REC
(i.e. factory-programmed). The reset output, RST, is active low or
active high, push-pull or open drain with optional pull-up resistor. The device fully operates
over a broad V
CC
range 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are ignored and
outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.
1.1 Test mode
After pull of SR0 up to V
TEST
or more (V
CC
+ 1.4 V, max.) we start counting initial shorten
t
SRC-INI
(42 ms, typ.). After t
SRC-INI
expires, the RST output either goes down for t
REC
(if
t
REC
option is used) or stays low as long as overvoltage on SR0 in detected (if t
REC
option is
not used). This is a feedback and a user knows that the device is locked in the test mode.
Each time both SR
inputs are connected to ground in test mode a shorten t
SRC-SHORT
(21
ms, typ.) is used instead of long t
SRC
(0.5 s -10 s). Return from to normal mode is possible
by a new startup of the device (i.e. V
CC
goes to 0 V and back to its original state). In this way
the device can be quickly tested without repeating test mode triggering. Advantage of this
solution is pretty high glitch immunity, feedback to user about entry to the test mode and
testability within full V
CC
range.