CY7C09269V/79V/89V
CY7C09369V/89V
Document Number: 38-06056 Rev. *M Page 18 of 25
Read/Write and Enable Operation
The Read/Write and Enable Operation is described as follows.
[51, 52, 53]
Inputs Outputs
Operation
OE CLK CE
0
CE
1
R/W I/O
0
–I/O
17
X H X X High Z Deselected
[54]
X X L X High Z Deselected
[54]
XLHLD
IN
Write
LLHHD
OUT
Read
[55]
H X L H X High Z Outputs Disabled
Address Counter Control Operation
The Address Counter Control Operation is described as follows.
[51, 56, 57, 58]
Address
Previous
Address
CLK ADS CNTEN CNTRST I/O Mode Operation
XX XXLD
out(0)
Reset Counter Reset to Address 0
A
n
XLXHD
out(n)
Load Address Load into Counter
XA
n
HH HD
out(n)
Hold External Address Blocked — Counter
Disabled
XA
n
HL HD
out(n+1)
Increment Counter Enabled — Internal Address
Generation
Notes
51. “X” = “Don’t Care”, “H” = V
IH
, “L” = V
IL
.
52. ADS
, CNTEN, CNTRST = “Don’t Care”.
53. OE
is an asynchronous input signal.
54. When CE
changes state in the pipelined mode, deselection and read happen in the following clock cycle.
55. ADS
= V
IL
, CNTEN and CNTRST = V
IH
.
56. CE
0
and OE = V
IL
; CE
1
and R/W = V
IH
.
57. Data shown for flow through mode; pipelined mode output is delayed by one cycle.
58. Counter operation is independent of CE
0
and CE
1
.
