74ACT646SC Datasheet 74ACT646SC, 74AC646SCX, 74AC646SC | P1-P3

November 1988

Revised October 2000

74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs

74AC646 • 74ACT646

Octal Transceiver/Register with 3-STATE Outputs

General Description

The AC/ACT646 consist of registered bus transceiver cir-

cuits, with outputs, D-type flip-flops and control circuitry

providing multiplexed transmission of data directly from the

input bus or from the internal storage registers. Data on the

A or B bus will be loaded into the respective registers on

the LOW-to-HIGH transition of the appropriate clock pin

(CPAB or CPBA). The four fundamental data handling

functions available are illustrated in Figures 1, 2, 3, and

Figure 4.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data transfers

■ 3-STATE outputs

■ 300 mil dual-in-line package

■ Outputs source/sink 24 mA

■ ACT646 has TTL compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74AC646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

74ACT646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74ACT646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

–A

Data Register A Inputs

Data Register A Outputs

–B

Data Register B Inputs

Data Register B Outputs

CPAB, CPBA Clock Pulse Inputs

SAB, SBA Transmit/Receive Inputs

Output Enable Input

DIR Direction Control Input

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74AC646 • 74ACT646

Function Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G

and DIR inputs. Data input functions are always enabled;

i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

Real Time Transfer

A-Bus to B-Bus

FIGURE 1.

Real Time Transfer

B-Bus to A-Bus

FIGURE 2.

Storage from

Bus to Register

FIGURE 3.

Transfer from

FIGURE 4.

Inputs Data I/O (Note 1)

Function

DIR CPAB CPBA SAB SBA

–A

–B

H X H or L H or L X X Isolation

X X X Input Input Clock A

Data into A Register

HXX

X X Clock B

Data into B Register

LHXXLX A

to B

—Real Time (Transparent Mode)

X L X Input Output Clock A

Data into A Register

L H H or L X H X A Register to B

(Stored Mode)

X H X Clock A

Data into A Register and Output to B

LLXXXL B

to A

—Real Time (Transparent Mode)

LLX

X L Output Input Clock B

Data into B Register

L L X H or L X H B Register to A

(Stored Mode)

LLX

X H Clock B

Data into B Register and Output to A

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74AC646 • 74ACT646

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

P1-P3 P4-P6 P7-P9

74ACT646SC

Mfr. #:

Buy 74ACT646SC

Manufacturer:

ON Semiconductor / Fairchild

Description:

Bus Transceivers Octal Bus Trans/Reg

Lifecycle:

New from this manufacturer.

Delivery:

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74ACT646SC

74ACT646SC

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