LTC3901
4
3901f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SYNC Negative Threshold vs
Temperature Propagation Delay vs V
CC
Propagation Delay vs
Temperature
Propagation Delay vs C
LOAD
Rise/Fall Time vs V
CC
Rise/Fall Time vs Temperature
Rise/Fall Time vs Load
Capacitance
Undervoltage Lockout Threshold
Voltage vs Temperature
TEMPERATURE (°C)
–50
SYNC NEGATIVE THRESHOLD (V)
100
3901 G07
050
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
–1.6
–1.7
–1.8
25 25 75 125
V
CC
(V)
4
PROPAGATION DELAY (µs)
10
3901 G08
68
120
110
100
90
80
70
60
50
40
57911
TEMPERATURE (°C)
50 100
3901 G09
05025 25 75 125
C
LOAD
(nF)
123 10
3901 G10
4567 98
RISE/FALL TIME (ns)
50
45
40
35
30
25
20
15
10
5
0
RISE/FALL TIME (ns)
50
45
40
35
30
25
20
15
10
5
0
3901 G11
TEMPERATURE (°C)
3901 G12
T
A
= 25°C
C
LOAD
= 4.7nF
T
A
= 25°C
C
LOAD
= 4.7nF
T
A
= 25°C
V
CC
= 5V
V
CC
= 5V
C
LOAD
= 4.7nF
V
CC
= 5V
C
LOAD
= 4.7nF
V
CC
= 5V, 11V
SYNC TO ME
SYNC TO MF
SYNC TO ME
SYNC TO MF
SYNC TO ME
SYNC TO MF
PROPAGATION DELAY (µs)
120
110
100
90
80
70
60
50
40
PROPAGATION DELAY (µs)
120
110
100
90
80
70
60
50
40
V
CC
(V)
410
6857911
FALL TIME
FALL TIME
RISE TIME
RISE TIME
C
LOAD
(nF)
1023 104567 98
RISE/FALL TIME (ns)
50
45
40
35
30
25
20
15
10
5
0
T
A
= 25°C
V
CC
= 5V
FALL TIME
RISE TIME
UNDERVOLTAGE LOCKOUT THRESHOLD
VOLTAGE (V)
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
3901 G143901 G13
TEMPERATURE (°C)
50 100
05025 25 75 125
FALLING EDGE
RISING EDGE
50 100
05025 25 75 125
LTC3901
5
3901f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
V
CC
Supply Current
vs Load Capacitance
C
LOAD
(nF)
1023 104567 98
T
A
= 25°C
3901 G16
V
CC
= 5V
V
CC
= 11V
SUPPLY CURRENT (mA)
30
25
20
15
10
5
0
P
V
CC
(Pin 1): Driver Supply Input. This pin powers the
ME and MF drivers. Bypass this pin to PGND using a 4.7µF
low ESR capacitor in close proximity to the LTC3901. This
pin should be connected to the same supply voltage as the
V
CC
pin.
ME (Pin 2, 3): Driver Output for ME. This pin drives the
gate of the external N-channel MOSFET, ME.
PGND (Pin 4,13): Power Ground. Both drivers return to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of ME and MF.
CSE
+
, CSE
(Pin 6, 5): ME Current Sense Differential
Input. Connect CSE
+
through a series resistor to the drain
of ME and CSE
through a series resistor to the source of
ME. The LTC3901 monitors the CSE inputs 250ns after ME
goes high. If the inductor current reverses and flows into
ME causing CSE
+
to rise above CSE
by more than 10.5mV,
the LTC3901 pulls ME low. See the Current Sense section
for more details on choosing the resistance values for
R
CSE1
to R
CSE3
.
TIMER (Pin 7): Timer Input. Connect this pin to an external
R-C network to program the timeout period. The LTC3901
resets the timer at every positive and negative transition of
the SYNC input. If the SYNC signal is missing or incorrect,
the LTC3901 pulls both ME and MF low once the TIMER
pin goes above the timeout threshold. See the Timer sec-
tion for more details on programming the timeout period.
GND (Pin 8,10): Signal Ground. All internal low power
circuitry returns to this pin. To minimize differential ground
currents, connect GND to PGND right at the LTC3901.
SYNC (Pin 9): Driver Synchronization Input. 0V at this pin
forces both ME and MF high after an initial negative pulse.
A subsequent positive pulse at SYNC input forces ME to
pull low, whereas a negative pulse forces MF to pull low.
The SYNC signal should alternate between positive and
negative pulses. If the SYNC signal is incorrect, the LTC3901
pulls both MF and ME low.
CSF
+
, CSF
(Pin 11, 12): MF Current Sense Differential
Input. Connect CSF
+
through a series resistor to the drain
of MF and CSF
through a series resistor to the source of
MF. The LTC3901 monitors the CSF inputs 250ns after MF
goes high. If the inductor current reverses and flows into
MF causing CSF
+
to rise above CSF
by more than 10.5mV,
the LTC3901 pulls MF low. See the Current Sense section
for more details on choosing the resistance values for
R
CSF1
to R
CSF3
.
MF (Pin 14, 15): Driver Output for MF. This pin drives the
gate of the external N-channel MOSFET, MF.
V
CC
(Pin 16): Power Supply Input. All internal circuits
except the drivers are powered from this pin. Bypass this
pin to GND using a 1µF capacitor in close proximity to the
LTC3901.
UU
U
PI FU CTIO S
V
CC
Supply Current vs
Temperature
3901 G15
TEMPERATURE (°C)
50 100
05025 25 75 125
C
LOAD
= 4.7nF
V
CC
SUPPLY CURRENT (mA)
20
18
16
14
12
10
8
6
4
V
CC
= 5V
V
CC
= 11V
LTC3901
6
3901f
BLOCK DIAGRA
W
APPLICATIO S I FOR ATIO
WUU
U
Figure 2. Push-Pull Converter Switching Waveforms
SYNC
AND
DRIVER
LOGIC
ISE
S
S
+
SYNC
+
SYNC
TMR
–1.4V
+1.4V
DISABLE
DRIVER
UVLO
Z
TMR
0.5 • V
CC
Z
CSE
11V
7
5
6
9
3
16
SYNC
CSE
+
CSE
ISF
Z
CSF
11V
12
11
CSF
+
CSF
TIMER
M
TMR
R1
180k
R2
45k
TIMER
RESET
ME
PGND
GND GND
MF
PGND
V
CC
1
PV
CC
14
4
13
108
3901 BD
+
+
10.5mV
10.5mV
DRVA
DRVB
SDRA
SDRB
SYNC
ME
3901 F02
MF
0V
Overview
Push-pull and full bridge converters use power transform-
ers to provide input-to-output isolation and voltage step-
up/down. Diodes are used as a simple solution for second-
ary side rectification. Unfortunately, as output currents
increase, the loss associated with diode forward voltage
drop results in low overall efficiency. The LTC3901 over-
comes this problem by providing control and drive for two
external N-channel synchronous MOSFETs. Synchroniza-
tion to the primary side controller is maintained through a
small signal transformer.
Figure 1 shows a simplified push-pull converter applica-
tion. T1 is the power transformer; MA and MB are the
primary side power transistors driven by the LTC3723
controller’s DRVA and DRVB outputs. The gate drive
transformer T2 is driven by the LTC3723’s SDRA and
SDRB outputs and provides the synchronization signal to
the LTC3901 on the secondary side. When both SDRA and
SDRB are high, there is no voltage across the transformer’s
primary and the LTC3901 SYNC input is approximately 0V.
According to the polarity of the transformer: if SDRA goes
low while SDRB is high, SYNC is positive; if SDRB goes
low while SDRA is high, SYNC is negative. ME and MF are
the secondary side synchronous switches driven by the
LTC3901’s ME and MF output. Inductor L1 and capacitor
C
OUT
form the output filter, providing DC output voltage to
the load. The feedback path from V
OUT
through the opto-
coupler driver and optocoupler back to the primary side
controller is also shown in Figure 1.
Each full cycle of the push-pull converter consists of four
distinct periods. Figure 2 shows the push-pull converter
waveforms.

LTC3901EGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers Synchronous Driver for Push-Pull Converters
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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