83947 Data Sheet
©2016 Integrated Device Technology, Inc Revision B March 17, 20164
TABLE 5. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 110 MHz
t
PD
Propagation Delay, NOTE 1
CLK to Q 1.8 4.5 ns
tsk(o) Output Skew; NOTE 2, 5
Measured on
rising edge @V
DDO
/2
500 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
Measured on
rising edge @V
DDO
/2
2ns
t
PW
Output Pulse Width tPeriod/2 - 800 tPeriod/2 + 800 ps
t
S
Clock Enable Setup Time; NOTE 6 CLK_EN to CLK 0 ns
t
H
Clock Enable Hold Time; NOTE 6 CLK_EN to CLK 1 ns
t
ZL
,
t
ZH
Output Enable Time; NOTE 4 11 ns
t
LZ
, t
HZ
Output Disable Time; NOTE 4 11 ns
t
R
Output Rise Time 0.8V to 2.0V 0.2 1 ns
t
F
Output Fall Time 0.8V to 2.0V 0.2 1 ns
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
