Low Skew, 1-to-9
LVCMOS Fanout Buffer
83947
Data Sheet
©2016 Integrated Device Technology, Inc Revision B March 17, 20161
GENERAL DESCRIPTION
The 83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series
or parallel terminated transmission lines. The effective fanout can be
increased from 9 to 18 byutilizing the ability of the outputs to drive two
series terminated lines.
Guaranteed output and part-to-part skew characteristics make the
83947I ideal for high performance, single ended applications that also
require a limited output voltage.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
9 LVCMOS/LVTTL outputs
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
Maximum output frequency: 110MHz
Output skew: 500ps (maximum)
Part-to-part skew: 2ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package available
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
GND
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
V
DD
GND
GND
Q6
V
DDO
Q7
GND
Q8
V
DDO
GND
GND
Q2
V
DDO
Q1
GND
Q0
V
DDO
GND
ICS83947I
83947 Data Sheet
©2016 Integrated Device Technology, Inc Revision B March 17, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Number Name Type Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
GND Power Power supply ground.
2 CLK_SEL Input Pullup
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7V
DD
Power Coree supply pin.
10, 14, 18, 22, 27, 31 V
DDO
Power Output supply pins.
11, 13, 15, 19, 21, 23,
26, 28, 30
Q8, Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Control Inputs Output
OE CLK_EN Q0:Q8
0 X Hi-Z
1 0 LOW
1 1 Follows CLK input
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
25 pF
R
PULLUP
Input Pullup Resistor 51
KΩ
R
PULLDOWN
Input Pulldown Resistor 51
KΩ
R
OUT
Output Impedance 5 7 12
Ω
83947 Data Sheet
©2016 Integrated Device Technology, Inc Revision B March 17, 20163
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Coret Supply Voltage 3.0 3.3 3.6 V
V
DDO
Output Supply Voltage 3.0 3.3 3.6 V
I
DD
Input Supply Current 33 50 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 3.6 V
V
IL
Input Low Voltage 0.8 V
I
IN
Input Current
CLK0, CLK1, CLK_SEL,
OE, CLK_EN
-100 µA
V
OH
Output High Voltage I
OH
= -20mA 2.5 V
V
OL
Output Low Voltage I
OL
= 20mA 0.4 V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.

83947AYILNT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 9 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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