MAX7359BETG+ Datasheet MAX7359ETG+, MAX7359ETG+T, MAX7359BETG+T | P13-P15

Only one autorepeat code is entered into the FIFO, regard-

less of the number of keys pressed. The autorepeat code

continues to be entered in the FIFO at the frequency set by

the bits D4–D1 until another key event is recorded.

Following the key-release event, if any keys are still

pressed, the MAX7359 restarts the autorepeat sequence.

Autosleep Register (0x06)

Autosleep puts the MAX7359 in sleep mode to draw minimal

current. When enabled, the MAX7359 enters sleep mode if

no keys are pressed for the autosleep time (Table 9).

Sleep Mode

In sleep mode, the MAX7359 draws minimal current.

Switch matrix current sources are turned off and pulled

up to V

. Writing a 0 to D7 in the configuration register

(0x01) puts the device in sleep mode. Writing a 1 to D7

or a key press, when the part is programmed to

autowake, can take the MAX7359 out of sleep mode.

Bit D7 in the configuration register gives the sleep

mode status and can be read anytime. The FIFO data is

maintained while in sleep mode.

Autowake

Key presses initiate autowake and the MAX7359 goes

into operating mode. Key presses that autowake the

MAX7359 are not lost. When a key is pressed while the

MAX7359 is in sleep mode, all analog circuitry, includ-

ing switch matrix current sources, turn on in 2ms. The

initial key needs to be pressed for 2ms plus the

debounce time to be stored in the FIFO. Autowakeup

can be disabled by writing a 0 to D1 in the configura-

tion register (0x01).

Serial Interface

Figure 1 shows the 2-wire serial interface timing details.

Serial Addressing

The MAX7359 operates as a slave that sends and

receives data through an I

C-compatible 2-wire inter-

face. The interface uses a serial-data line (SDA) and a

serial-clock line (SCL) to achieve bidirectional commu-

nication between master(s) and slave(s). A master (typ-

ically a microcontroller) initiates all data transfers to and

from the MAX7359 and generates the SCL clock that

synchronizes the data transfer.

The MAX7359’s SDA line operates as both an input and

an open-drain output. A pullup resistor, typically 4.7kΩ,

is required on SDA. The MAX7359’s SCL line operates

only as an input. A pullup resistor is required on SCL if

there are multiple masters on the 2-wire interface, or if

the master in a single-master system has an open-drain

SCL output.

Each transmission consists of a START (S) condition

(Figure 2) sent by a master, followed by the MAX7359 7-

bit slave address plus R/W bit, a register address byte, 1

or more data bytes, and finally a STOP (P) condition.

START and STOP Conditions

Both SCL and SDA remain high when the interface is not

busy. A master signals the beginning of a transmission

with a START condition by transitioning SDA from high to

low while SCL is high. When the master has finished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

Bit Transfer

One data bit is transferred during each clock pulse

(Figure 3). The data on SDA must remain stable while

SCL is high.

MAX7359

2-Wire Interfaced Low-EMI

Key Switch Controller/GPO

______________________________________________________________________________________ 13

RESERVED AUTOSHUTDOWN TIME

AUTOSLEEP REGISTER

D7 D6 D5 D4 D3 D2 D1 D0

No Autosleep 0 0 0 0 0 0 0 0

Autosleep for (ms)

8192 0 0 0 0 0 0 0 1

4096 0 0 0 0 0 0 1 0

2048 0 0 0 0 0 0 1 1

1024 0 0 0 0 0 1 0 0

512 00000 1 0 1

256 00000 1 1 0

256 00000 1 1 1

Power-up default settings 0 0 0 0 0 1 1 1

Table 9. Autosleep Register Format (0x06)

MAX7359

2-Wire Interfaced Low-EMI

Key Switch Controller/GPO

14 ______________________________________________________________________________________

SDA

SCL

HD, STA

LOW

HIGH

SU, DAT

SU, STA

SU, STO

BUF

HD, STA

HD, DAT

START

CONDITION

STOP

CONDITION

START

CONDITION

REPEATED

START CONDITION

F, TX

Figure 1. 2-Wire Serial Interface Timing Details

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 2. START and STOP Conditions

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 3. Bit Transfer

MAX7359

2-Wire Interfaced Low-EMI

Key Switch Controller/GPO

______________________________________________________________________________________ 15

MAX7359

Acknowledge

The acknowledge bit is a clocked 9th bit (Figure 4),

which the recipient uses to handshake receipt of each

byte of data. Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse, so the SDA line is stable low

during the high period of the clock pulse. When the

master is transmitting to the MAX7359, the MAX7359

generates the acknowledge bit because the MAX7359

is the recipient. When the MAX7359 is transmitting to

the master, the master generates the acknowledge bit

because the master is the recipient.

Slave Addresses

The MAX7359 has a 7-bit long slave address (Figure 5).

The bit following a 7-bit slave address is the R/W bit,

which is low for a write command and high for a read

command.

The first 4 bits (MSBs) of the MAX7359 slave address

are always 0111. Slave address bits A3, A2, and A1

correspond, by the matrix in Table 10, to the states of

the device address input AD0, and A0 corresponds to

the R/W bit. The AD0 input can be connected to any of

four signals: GND, V

, SDA, or SCL, giving four possi-

ble slave address pairs, allowing up to four MAX7359

devices to share the bus. Because SDA and SCL are

dynamic signals, care must be taken to ensure that AD0

transitions no sooner than the signals on the SDA and

SCL pins.

The MAX7359 monitors the bus continuously, waiting for

a START condition followed by its slave address. When

the MAX7359 recognizes its slave address, it acknowl-

edges and is then ready for continued communication.

Bus Timeout

The MAX7359 features a 20ms minimum bus timeout on

the 2-wire serial interface, largely to prevent the

MAX7359 from holding the SDA I/O low during a read

transaction if the SCL hangs for any reason before a seri-

al transaction has been completed. Bus timeout operates

by causing the MAX7359 to internally terminate a serial

transaction, either read or write, if SCL low exceeds

20ms. After a bus timeout, the MAX7359 waits for a valid

START condition before responding to a consecutive

transmission. This feature can be enabled or disabled

under user control by writing to the configuration register

(Table 4).

DEVICE ADDRESS

PIN AD0

A7 A6 A5 A4 A3 A2 A1 A0

GND 0111000R/W

0111010R/W

SDA 0111100R/W

SCL 0111110R/W

Table 10. 2-Wire Interface Address Map

SDA

SCL

01 1A3A2A11

MSB

LSB

ACKR/W

Figure 5. Slave Address

SCL

SDA

TRANSMITTER

CLOCK PULSE FOR

ACKNOWLEDGE

START

CONDITION

SDA

RECEIVER

1 2 8 9

Figure 4. Acknowledge

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX7359BETG+

Mfr. #:

Buy MAX7359BETG+

Manufacturer:

Maxim Integrated

Description:

IC KEY SWITCH 2WIRE 24TQFN

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MAX7359BETG+

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