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M48Z32V Operating modes
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2 Operating modes
The M48Z32V also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single power supply for an out of tolerance condition. When V
CC
is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below
approximately V
SO
, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2. Operating modes
Note: X = V
IH
or V
IL
; V
SO
= Battery back-up switchover voltage.
2.1 Read mode
The M48Z32V is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. The device architecture allows ripple-through access of data from eight of 262,144
locations in the static storage array. Thus, the unique address specified by the 15 Address
Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Access time (t
AVQV
) after the last address input
signal is stable, providing that the E
and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the Chip Enable
Access time (t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals is controlled by E
and G. If the outputs are
activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If
the Address Inputs are changed while E
and G remain active, output data will remain valid
for Output Data Hold time (t
AXQX
) but will go indeterminate until the next Address Access.
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
3.0 to 3.6V
V
IH
X X High Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High Z Active
Deselect V
SO
to V
PFD
(min)
(1)
1. See Table 12 on page 15 for details.
X X X High Z CMOS standby
Deselect ≤ V
SO
(1)
X X X High Z
Battery back-up
mode
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