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8501BYLFT

P1-P3P4-P6P7-P9P10-P11
Integrated
Circuit
Systems, Inc.
ICS8501
LOW SKEW, 1-TO-16 DIFFERENTIAL CURRENT MODE
FANOUT BUFFER
8501BY www.icst.com/products/hiperclocks.html REV. B OCTOBER 3, 2003
4
TABLE 5. HCSL AC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO
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egatlovtuptuokaep-ot-kaepeht
005zHM
pt
,HL
;yaleDnoitagaporP
hgiH-ot-woL
f<0 ≤ zHM0522 3sn
pt
LH
;yaleDnoitagaporP
woL-ot-hgiH
f<0 ≤ zHM0522 3sn
t
)o(ks3,1ETON;wekStuptuOXOVtanoderusaeM001sp
t
)pp(ks
;wekStraP-ot-traP
3,2ETON
XOVtanoderusaeM056sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02571007sp
t
WP
htdiWesluPtuptuOt
DOIREP
3.0-2/t
DOIREP
2/t
DOIREP
3.0+2/sn
VroftestsujdatnerruC
HO
.ylnostuptuoXEICPotreferstnemerusaeM.V7.0=
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuonee
wtebwekssadenifeD:1ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
htiwdnasegatlovylppusemasehttagnita
reposecivedtnereffidnostuptuoneewtebweksehtsadenifeD:2ETON
Vtaderusaemerastuptuoeht,ecivedhcaenostupni
foepytemasehtgnisU.snoitidnocdaollauqe
DD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:3ETON
Integrated
Circuit
Systems, Inc.
ICS8501
LOW SKEW, 1-TO-16 DIFFERENTIAL CURRENT MODE
FANOUT BUFFER
8501BY www.icst.com/products/hiperclocks.html REV. B OCTOBER 3, 2003
5
SCOPE
Qx
HCSL
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
0V
PART-TO-PART SKEW
OUTPUT PULSE WIDTH/PERIOD
3.3V±5%
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
t
sk(o)
nQx
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
Qx
nQy
Qy
HCSL OUTPUT RISE/FALL TIME
Pulse Width
t
PERIOD
Q0:Q15
nQ0:nQ15
V
DD
GND
t
sk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
Integrated
Circuit
Systems, Inc.
ICS8501
LOW SKEW, 1-TO-16 DIFFERENTIAL CURRENT MODE
FANOUT BUFFER
8501BY www.icst.com/products/hiperclocks.html REV. B OCTOBER 3, 2003
6
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
P1-P3P4-P6P7-P9P10-P11

8501BYLFT

Mfr. #:
Buy 8501BYLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 16 HCSL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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