REV. B
AD7470/AD7472
–17–
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between the analog
and digital sections within the device. To complement the excel-
lent noise performance of the AD7470/AD7472, it is imperative
that care be given to the PCB layout. Figure 16 shows a recom-
mended connection diagram for the AD7470/AD7472.
All of the AD7470/AD7472 ground pins should be soldered
directly to a ground plane to minimize series inductance. The
AV
DD
, DV
DD
,
and V
DRIVE
pins should be decoupled to both the
analog and digital ground planes. The large value capacitors will
decouple low frequency noise to analog ground; the small value
capacitors will decouple high frequency noise to digital ground.
All digital circuitry power pins should be decoupled to the
digital ground plane. The use of ground planes can physically
separate sensitive analog components from the noisy digital
system. The two ground planes should be joined in only one
place and should not overlap so as to minimize capacitive
coupling between them. If the AD7470/AD7472 is in a
system where multiple devices require AGND to DGND
connections, the connection should still be made at one point
only, a star ground point, which should be established as close
as possible to the AD7470/AD7472.
Noise can be minimized by applying some simple rules to the
PCB layout: analog signals should be kept away from digital
signals; fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of the
board and clock signals should never be run near the analog
inputs; avoid running digital lines under the device as these will
couple noise onto the die; the power supply lines to the AD7470/
AD7472 should use as large a trace as possible to provide a low
impedance path and reduce the effects of glitches on the power
supply line; avoid crossover of digital and analog signals and
place traces that are on opposite sides of the board at right angles
to each other.
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 16. Decou-
pling capacitors should be placed directly at the power inlet to
the PCB and also as close as possible to the power pins of the
AD7470/AD7472. The same decoupling method should be
used on other ICs on the PCB, with the capacitor leads as short
as possible to minimize lead inductance.
POWER SUPPLIES
Separate power supplies for AV
DD
and DV
DD
are desirable but,
if necessary, DV
DD
may share its power connection to AV
DD
.
The digital supply (DV
DD
) must not exceed the analog supply
(AV
DD
) by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
AD7470/AD7472 to ADSP-2185 Interface
Figure 17 shows a typical interface between the AD7470/AD7472
and the ADSP-2185. The ADSP-2185 processor can be used in
one of two memory modes, full memory mode and host mode.
The Mode C pin determines in which mode the processor works.
The interface in Figure 17 is set up to have the processor work-
ing in full memory mode, which allows full external addressing
capabilities.
When the AD7470/AD7472 has finished converting, the BUSY
line requests an interrupt through the IRQ2 pin. The IRQ2
interrupt has to be set up in the interrupt control register as
edge-sensitive. The DMS (data memory select) pin latches in
the address of the ADC into the address decoder. The read
operation is thus started.
ADDRESS
DECODER
AD7470/
AD7472*
ADSP-2185*
A0–A15
DMS
IRQ2
RD
MODE C
D0–D23
CONVST
CS
RD
BUSY
DB0–DB9
(DB11)
ADDRESS BUS
DATA BUS
100k⍀
*ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
Figure 17. Interfacing to the ADSP-2185
AD7470/AD7472 to ADSP-21065 Interface
Figure 18 shows a typical interface between the AD7470/AD7472
and the ADSP-21065L SHARC
®
processor. This interface is an
example of one of three DMA handshake modes. The MSX
AD7470/
AD7472
AD780
10F
+
1nF
V
IN
V
OUT
1nF
+
10F
0.1F
10F
DV
DD
AGND
DGND
V
DRIVE
V
REF
AV
DD
+
0.1F47F
ANALOG
SUPPLY
5V
+
0.1F
Figure 16. Decoupling Circuit
