OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SC28L91A1A,529

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
22
REGISTER DESCRIPTIONS MODE REGISTERS
MR0 – Mode Register 0
Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
Addr Bit 7 BIT 6 BITS 5:4 BIT 3 BIT 2 BIT 1 BIT 0
MR0 Rx
WATCHDOG
RxINT BIT 2 TxINT (1:0) FIFO SIZE BAUD RATE
EXTENDED II
TEST 2 BAUD RATE
EXTENDED 1
0x00
0x08
0 = Disable
1 = Enable
See Tables in
MR0 descrip-
tion
See Table 4 0 = 8 byte FIFO
1 = 16 byte FIFO
0 = Normal
1 = Extend II
Set to 0 0 = Normal
1 = Extend
MR0[7]—Watchdog Control
This bit controls the receiver watchdog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6]—Rx Interrupt bit 2
Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1
sets the fill level of the FIFO that generates the receiver interrupt.
MR0[6], MR1[6] Rx Interrupt bits
Note that this control is split between MR0 and MR1. This is for
backward compatibility to legacy software of the SC2692 and
SCN2681 dual UART devices.
Table 3. Receiver FIFO
Interrupt fill level (MR0(3) = 0 (8 bytes)
MR0[6] MR1[6] Interrupt Condition
00 1 or more bytes in FIFO (Rx RDY)
01 6 or more bytes in FIFO
10 4 or more bytes in FIFO
11 8 bytes in FIFO (Rx FULL)
Table 3a. Receiver FIFO
Interrupt fill level(MR0(3)=1 (16 bytes)
MR0[6] MR1[6] Interrupt Condition
00 1 or more bytes in FIFO (Rx RDY)
01 8 or more bytes in FIFO
10 12 or more bytes in FIFO
11 16 bytes in FIFO (Rx FULL)
For the receiver these bits control the number of FIFO positions
filled when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4]—Tx interrupt fill level.
Table 4. Transmitter FIFO
Interrupt fill level MR0(3) = 0 (8 bytes)
MR0[5:4] Interrupt Condition
00 8 bytes empty (Tx EMPTY)
01 4 or more bytes empty
10 6 or more bytes empty
11 1 or more bytes empty (Tx RDY)
Table 4a. Transmitter FIFO
Interrupt fill level MR0(3) = 1 (16 bytes)
MR0[5:4] Interrupt Condition
00 16 bytes empty (Tx EMPTY)
01 8 or more bytes empty
10 12 or more bytes empty
11 1 or more bytes empty (Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the transmitter will attempt to interrupt. After the reset
the transmit FIFO has 8 bytes empty. It will then attempt to interrupt
as soon as the transmitter is enabled. The default setting of the MR0
bits [5:4] condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one–byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3]—FIFO size
Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4
MR0[2:0]—Baud Rate Group Selection
These bits are used to select one of the six–baud rate groups.
See Table 5 for the group organization.
• 000 Normal mode
• 001 Extended mode I
• 100 Extended mode II
Other combinations of MR2[2:0] should not be used.
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
23
MR1 – Mode Register 1
Addr BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR1 Rx CONTROLS
RTS
RxINT
BIT 1
ERROR
MODE
PARITY MODE PARITY TYPE BITS PER
CHARACTER
0x00 0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multi-drop Mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR1 is accessed when the MR pointer points to MR1. The pointer is
set to MR1 by RESET or by a ‘set pointer’ command applied via CR
command 0x10. After reading or writing MR1, the pointer will point to
MR2 and will not move from MR2 on subsequent MR reads or
writes.
MR1[7]— Receiver Request–to–Send Control (Flow Control)
This bit controls the deactivation of the RTSN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. Proper automatic operation of flow
control requires OPR[0] to be set to logical 1.
MR1[7] = 1 causes RTSN to be negated (OP0 is driven to a ‘1’
[V
CC
]) upon receipt of a valid start bit if the FIFO is full. This is the
beginning of the reception of the ninth byte. If the FIFO is not read
before the start of the tenth or 17th byte, an overrun condition will
occur and the tenth or 17th or 17th byte will be lost. However, the bit
in OPR[0] is not reset and RTSN will be asserted again when an
empty FIFO position is available. This feature can be used for flow
control to prevent overrun in the receiver by using the RTSN output
signal to control the CTSN input of the transmitting device.
MR1[6]—Rx Interrupt Bit 1
Bit 1 of the receiver interrupt control. See description under MR0[6].
MR1[5]— Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, and received break) for. In the ‘character’ mode, status is
provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the ‘block’ mode, the
status provided in the SR for these bits is the accumulation
(logical-OR) of the status for all characters coming to the top of the
FIFO since the last ‘reset error’ command was issued.
MR1[4:3|— Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1[4:3] = 11 selects operation in the special
multi–drop mode described in the Operation section.
MR1[2]— Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multi-drop mode it
selects the polarity of the A/D bit.
MR1[1:0]— Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
24
MR2 – Mode Register 2
MR2 is accessed when the MR pointer points to MR2, which occurs after any access to MR1. Accesses to MR2 do not change the pointer.
ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR CHANNEL MODE Tx CONTROLS
RTS
CTS
ENABLE Tx
STOP BIT LENGTH
NOTE: Add 0.5 to binary codes 0–7 for 5 bit character lengths.
0x00
00 = Normal 0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
01 = Auto-Echo 0 = No 0 = No 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875
10 = Local loop 1 = Yes 1 = Yes 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
11 = Remote loop 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE:
Add 0.5 to values shown for 0–7 if channel is programmed for 5 bits/char.
MR2[7:6]— Mode Select
The channel of the UART can operate in one of four modes.
MR2[7:6] = 00 is the normal mode, with the transmitter and receiver
operating independently.
MR2[7:6] = 01 places the channel in the automatic echo mode,
which automatically retransmits the received data. The following
conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter needs not be
enabled.
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for
transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
MR2[7:6] = 10 selects local loop back diagnostic mode. In this
mode:
1. The transmitter output is internally connected to the receiver
input.
2. The transmit clock is used for the receiver.
3. The TxD output is held High.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue
normally.
MR2[7:6] = 11 selects remote loop back diagnostic mode. In this
mode:
1. Received data is reclocked and retransmitted on the TxD
out–put.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are
retransmitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately.
An exception to this occurs when switching out of auto echo or
remote loop back modes. If the de-selection occurs just after the
receiver has sampled the stop bit (indicated in auto echo by
assertion of RxRDY) and the transmitter is enabled, then the
transmitter will remain in auto echo mode until the stop bit(s) have
been re-transmitted.
In most situations the above is rendered transparent by other
system considerations. However recall that the stop bit sequence
may be very long compared to bus cycles. If rapid reconfiguration of
the transmitter is desired in the above conditions the controlling
system should wait for the TxEMT bit to set or issue a Tx software
reset before reconfiguration begins.
MR2[5]— Transmitter Request–to–Send Control
This bit controls the deactivation of the RTSN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR2[5] = 1 caused OPR[0] to be
reset automatically one bit time after the characters in the transmit
shift register and in the TxFIFO, if any, are completely transmitted
including the programmed number of stop bits, if the transmitter is
not enabled.
This feature can be used to automatically terminate the transmission
of a message as follows (“line turnaround”):
1. Program auto–reset mode: MR2[5] = 1.
2. Enable transmitter.
3. Asset RTSN: OPR[0] = 1.
4. Send message.
5. Disable transmitter after the last character is loaded into the
TxFIFO.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

SC28L91A1A,529

Mfr. #:
Buy SC28L91A1A,529
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 44-PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet