MPC99J93 REVISION 4 FEBRUARY 6, 2013 6 ©2013 Integrated Device Technology, Inc.
MPC99J93 Data Sheet INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS) PLL CLOCK DRIVER
APPLICATIONS INFORMATION
The MPC99J93 is a dual clock PLL with on-chip Intelligent
Dynamic Clock Switch (IDCS) circuitry.
Definitions
primary clock: The input CLK selected by Sel_Clk.
secondary clock: The input CLK NOT selected by
Sel_Clk.
PLL reference signal: The CLK selected as the PLL
reference signal by Sel_Clk or IDCS. (IDCS can override
Sel_Clk).
Status Functions
Clk_Selected: Clk_Selected (L) indicates CLK0 is
selected as the PLL reference signal. Clk_Selected (H)
indicates CLK1 is selected as the PLL reference signal.
INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for
at least one Ext_FB period (Pos to Pos or Neg to Neg).
Cleared (L) on assertion of Alarm_Reset
.
Control Functions
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock.
Sel_Clk (H) selects CLK1 as the primary clock.
Alarm_Reset
: Asserted by a negative edge. Generates a
one-shot reset pulse that clears INPUT_BAD latches and
Clk_Selected latch.
PLL_En: While (L), the PLL reference signal is substituted
for the VCO output.
MR
: While (L), internal dividers are held in reset which
holds all Q outputs LOW.
Man Override (H)
(IDCS is disabled, PLL functions normally). PLL reference
signal (as indicated by Clk_Selected) will always be the CLK
selected by Sel_Clk. The status function INP_BAD is active
in Man Override (H) and (L).
Man Override (L)
(IDCS is enabled, PLL functions enhanced). The first CLK
to fail will latch it's INP_BAD (H) status flag and select the
other input as the Clk_Selected for the PLL reference clock.
Once latched, the Clk_Selected and INP_BAD remain
latched until assertion of Alarm_Reset
which clears all
latches (INP_BADs are cleared and Clk_Selected = Sel_Clk).
NOTE: If both CLKs are bad when Alarm_Reset
is asserted,
both INP_BADs will be latched (H) after one Ext_FB period
and Clk_Selected will be latched (L) indicating CLK0 is the
PLL reference signal. While neither INP_BAD is latched (H),
the Clk_Selected can be freely changed with Sel_Clk.
Whenever a CLK switch occurs, (manually or by IDCS),
following the next negative edge of the newly selected PLL
reference signal, the next positive edge pair of Ext_FB and
the newly selected PLL reference signal will slew to
alignment.
To calculate the overall uncertainty between the input
CLKs and the outputs from multiple MPC99J93's, the
following procedure should be used. Assuming that the input
CLKs to all MPC9993's are exactly in phase, the total
uncertainty will be the sum of the static phase offset, max I/O
jitter, and output to output skew.
During a dynamic switch, the output phase between two
devices may be increased for a short period of time. If the two
input CLKs are 400ps out of phase, a dynamic switch of an
MPC99J93 will result in an instantaneous phase change of
400ps to the PLL reference signal without a corresponding
change in the output phase (due to the limited response of
the PLL). As a result, the I/O phase of a device, undergoing
this switch, will initially be 400ps and diminish as the PLL
slews to its new phase alignment. This transient timing issue
should be considered when analyzing the overall skew
budget of a system.
Hot insertion and withdrawal
In PECL applications, a powered up driver will experience
a low impedance path through an MPC99J93 input to its
powered down V
CC
pins. In this case, a 100 ohm series
resistance should be used in front of the input pins to limit the
driver current. The resistor will have minimal impact on the
rise and fall times of the input signals.
Acquiring Frequency Lock
1. While the MPC99J93 is receiving a valid CLK signal,
assert Man_Override HIGH.
2. The PLL will phase and frequency lock within the
specified lock time.
3. Apply a HIGH to LOW transition to Alarm_Reset to reset
Input Bad flags.
4. De-assert Man_Override LOW to enable Intelligent
Dynamic Clock Switch mode.
