MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
10
Maxim Integrated
The adaptive driver dead-time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from DL and DH to
the MOSFET gates for the adaptive dead-time circuits
to function properly. The stray impedance in the gate
discharge path can cause the sense circuitry to inter-
pret the MOSFET gate as off while the V
GS
of the
MOSFET is still high. To minimize stray impedance, use
very short, wide traces.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch. The
MAX15026 features a robust internal pulldown transis-
tor with a typical 1 R
DS(ON)
to drive DL low. This low
on-resistance prevents DL from being pulled up during
the fast rise time of the LX node, due to capacitive cou-
pling from the drain to the gate of the low-side synchro-
nous rectifier MOSFET.
High-Side Gate-Drive Supply (BST)
and Internal Boost Switch
An internal switch between BST and DH turns on to
boost the gate voltage above V
IN
providing the neces-
sary gate-to-source voltage to turn on the high-side
MOSFET. The boost capacitor connected between BST
and LX holds up the voltage across the gate driver dur-
ing the high-side MOSFET on-time.
The charge lost by the boost capacitor for delivering the
gate charge is replenished when the high-side MOSFET
turns off and LX node goes to ground. When LX is low,
an internal high-voltage switch connected between
V
DRV
and BST recharges the boost capacitor. See the
Boost Capacitor
section in the
Applications Information
to choose the right size of the boost capacitor.
Enable Input (EN), Soft-Start,
and Soft-Stop
Drive EN high to turn on the MAX15026. A soft-start
sequence starts to increase step-wise the reference
voltage of the error amplifier. The duration of the soft-
start ramp is 2048 switching cycles and the resolution
is 1/64th of the steady-state regulation voltage allowing
a smooth increase of the output voltage. A logic-low on
EN initiates a soft-stop sequence by stepping down the
reference voltage of the error amplifier. After the soft-
stop sequence is completed, the MOSFET drivers are
both turned off. See Figure 1. The soft-stop feature is
disabled in the MAX15026D.
Connect EN to V
CC
for always-on operation. Owing to
the accurate turn-on/-off thresholds, EN can be used as
UVLO adjustment input, and for power sequencing
together with the PGOOD output.
When the valley current limit is reached during soft-start
the MAX15026 regulates to the output impedance times
the limited inductor current and turns off after 4096
clock cycles. When starting up into a large capacitive
load (for example) the inrush current will not exceed the
current-limit value. If the soft-start is not completed
before 4096 clock cycles, the device will turn off. The
device remains off for 8192 clock cycles before trying
to soft-start again. This implementation allows the soft-
start time to be automatically adapted to the time nec-
essary to keep the inductor current below the limit while
charging the output capacitor.
Power-Good Output (PGOOD)
The MAX15026 includes a power-good comparator to
monitor the output voltage and detect the power-good
threshold, fixed at 94.5% of the nominal FB voltage. The
open-drain PGOOD output requires an external pullup
resistor. PGOOD sinks up to 2mA of current while low.
PGOOD goes high (high-impedance) when the regula-
tor output increases above 94.5% of the designed nom-
inal regulated voltage. PGOOD goes low when the
regulator output voltage drops to below 92% of the
nominal regulated voltage. PGOOD asserts low during
hiccup timeout period.
Startup into a Prebiased Output
When the MAX15026 starts into a prebiased output, DH
and DL are off so that the converter does not sink cur-
rent from the output. DH and DL do not start switching
until the PWM comparator commands the first PWM
pulse. The first PWM pulse occurs when the ramping
reference voltage increases above the FB voltage.
MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
11
Maxim Integrated
Current-Limit Circuit (LIM)
The current-limit circuit employs a valley and sink cur-
rent-sensing algorithm that uses the on-resistance of
the low-side MOSFET as a current-sensing element, to
eliminate costly sense resistors. The current-limit circuit
is also temperature compensated to track the on-resis-
tance variation of the MOSFET over temperature. The
current limit is adjustable with an external resistor at
LIM, and accommodates MOSFETs with a wide range
of on-resistance characteristics (see the
Setting the
Valley Current Limit
section). The adjustment range is
from 30mV to 300mV for the valley current limit, corre-
sponding to resistor values of 6k to 60k. The valley
current-limit threshold across the low-side MOSFET is
precisely 1/10th of the voltage at LIM, while the sink
current-limit threshold is 1/20th of the voltage at LIM.
Valley current limit acts when the inductor current flows
towards the load, and LX is more negative than GND
during the low-side MOSFET on-time. If the magnitude
of current-sense signal exceeds the valley current-limit
threshold at the end of the low-side MOSFET on-time,
the MAX15026 does not initiate a new PWM cycle and
lets the inductor current decay in the next cycle. The
controller also rolls back the internal reference voltage
so that the controller finds a regulation point deter-
mined by the current-limit value and the resistance of
the short. In this manner, the controller acts as a con-
stant current source. This method greatly reduces
inductor ripple current during the short event, which
reduces inductor sizing restrictions, and reduces the
possibility for audible noise. After a timeout, the device
goes into hiccup mode. Once the short is removed, the
internal reference voltage soft-starts back up to the nor-
mal reference voltage and regulation continues.
V
CC
B
CD
E
2048 CLK
CYCLES
2048 CLK
CYCLES
F
G
HIA
UVLO
EN
V
OUT
DAC_VREF
DH
DL
UVLO
Undervoltage threshold value is provided in
the Electrical Characteristics table.
Internal 5.25V linear regulator output.
Active-high enable input.
Regulator output voltage.
Regulator internal soft-start and soft-stop signal.
Regulator high-side gate-driver output.
Regulator low-side gate-driver output.
V
CC
rising while below the UVLO threshold.
EN is low.
V
CC
EN
V
OUT
DAC_VREF
DH
DL
A
SYMBOL DEFINITION
B
V
CC
is higher than the UVLO threshold. EN is low.
EN is pulled high. DH and DL start switching.
Normal operation.
V
CC
drops below UVLO.
V
CC
goes above the UVLO threshold. DH and DL
start switching. Normal operation.
EN is pulled low. V
OUT
enters soft-stop.
EN is pulled high. DH and DL start switching.
Normal operation.
V
CC
drops below UVLO.
C
D
E
F
G
H
I
SYMBOL DEFINITION
Figure 1. Power-On/-Off Sequencing for MAX15026B/C.
MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
12
Maxim Integrated
Sink current limit is implemented by monitoring the volt-
age drop across the low-side MOSFET when LX is more
positive than GND. When the voltage drop across the
low-side MOSFET exceeds 1/20th of the voltage at LIM
at any time during the low-side MOSFET on-time, the
low-side MOSFET turns off, and the inductor current
flows from the output through the body diode of the high-
side MOSFET. When the sink current limit activates, the
DH/DL switching sequence is no longer complementary.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-
sense signals at LX and GND. Mount the MAX15026
close to the low-side MOSFET with short, direct traces
making a Kelvin-sense connection so that trace resis-
tance does not add to the intended sense resistance of
the low-side MOSFET.
Hiccup-Mode Overcurrent Protection
Hiccup-mode overcurrent protection reduces power dis-
sipation during prolonged short-circuit or deep overload
conditions. An internal three-bit counter counts up on
each switching cycle when the valley current-limit
threshold is reached. The counter counts down on each
switching cycle when the threshold is not reached, and
stops at zero (000). The counter reaches 111 (= 7
events) when the valley mode current-limit condition
persists. The MAX15026 stops both DL and DH drivers
and waits for 4096 switching cycles (hiccup timeout
delay) before attempting a new soft-start sequence. The
hiccup-mode protection remains active during the soft-
start time.
Undervoltage Lockout
The MAX15026 provides an internal undervoltage lockout
(UVLO) circuit to monitor the voltage on V
CC
. The UVLO
circuit prevents the MAX15026 from operating when V
CC
is lower than V
UVLO
. The UVLO threshold is 4V, with
400mV hysteresis to prevent chattering on the rising/falling
edge of the supply voltage. DL and DH stay low to inhibit
switching when the device is in undervoltage lockout.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the MAX15026. When the junction temperature of the
device exceeds +150°C, an on-chip thermal sensor shuts
down the device, forcing DL and DH low, allowing the
device to cool. The thermal sensor turns the device on
again after the junction temperature cools by 20°C. The
regulator shuts down and soft-start resets during thermal
shutdown. Power dissipation in the LDO regulator and
excessive driving losses at DH/DL trigger thermal-over-
load protection. Carefully evaluate the total power dissi-
pation (see the
Power Dissipation
section) to avoid
unwanted triggering of the thermal-overload protection in
normal operation.
Applications Information
Effective Input Voltage Range
The MAX15026 operates from input supplies up to 28V
and regulates down to 0.6V. The minimum voltage con-
version ratio (V
OUT
/V
IN
) is limited by the minimum con-
trollable on-time. For proper fixed-frequency PWM
operation, the voltage conversion ratio must obey the
following condition,
where t
ON(MIN)
is 125ns and f
SW
is the switching fre-
quency in Hertz. Pulse-skipping occurs to decrease the
effective duty cycle when the desired voltage conver-
sion does not meet the above condition. Decrease the
switching frequency or lower V
IN
to avoid pulse skipping.
The maximum voltage conversion ratio is limited by the
maximum duty cycle (D
max
):
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistance. V
DROP2
is the
sum of the resistance in the charging path, including
high-side switch, inductor, and PCB resistance. In
practice, provide adequate margin to the above condi-
tions for good load-transient response.
Setting the Output Voltage
Set the MAX15026 output voltage by connecting a
resistive divider from the output to FB to GND (Figure
2). Select R
2
from between 1k and 50k. Calculate
R
1
with the following equation:
where V
FB
= 0.591V (see the
Electrical Characteristics
table) and V
OUT
can range from 0.591V to (0.85 x V
IN
).
Resistor R
1
also plays a role in the design of the Type III
compensation network. Review the values of R
1
and R
2
when using a Type III compensation network (see the
Type III Compensation Network (See Figure 4)
section).
RR
V
V
OUT
FB
12
1=
V
V
D
DV (1D)V
V
OUT
IN
max
max DROP2 max DROP1
IN
<
×+ ×
V
V
tf
OUT
N
ON(MIN) SW
I

MAX15026CETD+G1D

Mfr. #:
Manufacturer:
Maxim Integrated
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