MAX9223/MAX9224
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
_______________________________________________________________________________________ 7
12
11
10
9
8
7
2.3 2.92.5 2.7 3.1 3.3 3.5
MAX9224
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc10
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
PCLKOUT = 10MHz
PCLKOUT = 5MHz
DOUT[21:0] = WORST-CASE SWITCHING
PATTERN
12
11
10
9
8
7
5678910
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc11
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
V
DD
= 3.3V
V
DD
= 2.8V
V
DD
= 2.5V
DOUT[21:0] = ALL LOW
12
11
10
9
8
7
5678910
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc12
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
V
DD
= 3.3V
V
DD
= 2.8V
V
DD
= 2.5V
DOUT[21:0] = ALL HIGH
150
120
90
60
30
0
0 0.2 0.4 0.6 0.8 1.0
MAX9224 DOUT OUTPUT-LOW VOLTAGE
vs. SINK CURRENT
MAX9233/4 toc16
SINK CURRENT (mA)
DOUT (mV)
V
DDO
= +1.71V TO +2.375V
160
140
120
100
80
2.3 2.92.5 2.7 3.1 3.3 3.5
MAX9224 DIFFERENTIAL INPUT
IMPEDANCE vs. SUPPLY VOLTAGE
MAX9233/4 toc17
SUPPLY VOLTAGE (V)
INPUT IMPEDANCE (Ω)
Typical Operating Characteristics (continued)
(V
DD
= V
DDO
= +2.8V, logic input levels = 0 to +2.8V, logic output load C
L
= 5pF, T
A
= +25°C, unless otherwise noted.)
12
11
10
9
8
7
5678910
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc13
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
V
DD
= 3.3V
V
DD
= 2.8V
V
DD
= 2.5V
DOUT[21:0] = WORST-CASE SWITCHING
PATTERN
0.6
0.5
0.4
0.3
0.2
2.3 2.92.5 2.7 3.1 3.3 3.5
MAX9224 POWER-DOWN
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc14
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
SDI+/SDI- PULLED UP TO V
DD
DOUT[21:0] = ALL LOW
2.75
2.50
2.25
2.00
1.75
1.50
1.25
0 0.2 0.4 0.6 0.8 1.0
MAX9224 DOUT OUTPUT-HIGH VOLTAGE
vs. SOURCE CURRENT
MAX9233/4 toc15
SOURCE CURRENT (mA)
DOUT (V)
V
DDO
= 2.375V
V
DDO
= 2V
V
DDO
= 1.71V
MAX9223/MAX9224
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
8 _______________________________________________________________________________________
Pin Description (MAX9223)
PIN NAME FUNCTION
1–12, 14, 15,
21–28
DIN13–DIN2,
DIN1, DIN0,
DIN21–DIN14
Single-Ended Parallel Data Inputs. The 22 data bits are loaded into the input latch on the rising
edge of PCLKIN. DIN[21:0] are 1.71V to 3.465V tolerant. Internally pulled down to GND.
13 PCLKIN
Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel
data input. Internally pulled down to GND.
16 PWRDN
Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode.
Drive PWRDN high for normal operation. Internally pulled down to GND.
17 SDO- Inverting LCDS Serial-Data Output
18 SDO+ Noninverting LCDS Serial-Data Output
19 GND Ground
20 V
DD
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
EP Exposed Paddle. Connect EP to ground.
Pin Description (MAX9224)
PIN NAME FUNCTION
1, 7, 8, 10–28
DOUT21,
DOUT0, DOUT1,
DOUT2–DOUT20
Single-Ended Parallel Data Outputs. DOUT[21:0] are valid on the rising edge of PCLKOUT.
2V
DDO
Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
3 GND Ground
4 SDI+ Noninverting LCDS Serial-Data Input
5 SDI- Inverting LCDS Serial-Data Input
6V
DD
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
9 PCLKOUT
Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically
the pixel clock).
EP Exposed Paddle. Connect EP to ground.
LCDS
The MAX9223/MAX9224 use a proprietary multilevel
LCDS interface. Figure 5 provides a representation of
the data and clock in the multilevel LCDS interface.
This interface offers advantages over other chipsets,
such as requiring only one differential pair as the trans-
mission medium, the inherently aligned data and clock,
and much smaller current levels than the 4mA typically
found in traditional LVDS interfaces.
MAX9223/MAX9224 Handshaking
The handshaking function of the MAX9223/MAX9224
provides bidirectional communication between the two
devices in case a word boundary error is detected. Prior
to data transmission, the MAX9223 serializer adds
boundary bits (OH) to the end of the latched word.
These boundary bits are the inverse of the last bit of the
latched word. During data transmission, the MAX9224
deserializer continuously monitors the state of the
boundary bits of each word. If a word boundary error is
detected, the serial link is pulled up to V
DD
and the
MAX9224 powers down. The MAX9223 detects the
pullup of the serial link and powers down for 1.0µs. After
1.0µs, the MAX9223 powers up, causing the power-up
of the MAX9224. Then the word boundary is reestab-
lished, and data transfer resumes. The handshaking
function is disabled when PWRDN is pulled low.
MAX9223/MAX9224
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
_______________________________________________________________________________________ 9
MAX9223 Functional Diagram
TIMING
AND
CONTROL
PARALLEL
TO
SERIAL
DLL
PWRDN
LATCH
INPUT
PCLKIN
DIN[21:0]
SDO+
SDO-
MAX9223
MAX9224 Functional Diagram
DOUT[21:0]
TIMING AND CONTROL
OUTPUT
LATCH
PCLKOUT
SERIAL
TO
PARALLEL
SDI+
SDI-
MAX9224
Detailed Description
The MAX9223 serializer operates at a 5MHz to 10MHz
parallel clock frequency, serializing 22 bits of parallel
input data DIN[21:0] in each cycle of the parallel clock.
DIN[21:0] are latched on the rising edge of PCLKIN.
The data and internally generated serial clock are com-
bined and transmitted through SDO+/SDO- using multi-
level LCDS. The MAX9224 deserializer receives the
LCDS signal on SDI+/SDI-. The deserialized data and
recovered parallel clock are available at DOUT[21:0]
and PCLKOUT. Output data is valid on the rising edge
of PCLKOUT.
The first bit (G) is internally grounded and transmitted
first. Bit 0 (DIN[0]) is the first valid data bit. Boundary
bits OH are used by the MAX9224 deserializer to identi-
fy the word boundary and are the inverse polarity of
data bit 21 (DIN[21]). Therefore, at least one level tran-
sition is guaranteed in one word. The clock is recov-
ered from the serial input.
G
0 1 2 3 4 5 6 7 8 9 101112131415161718192021OH
OH
Serial word format:

MAX9224ETI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipsets
Lifecycle:
New from this manufacturer.
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