©2011 Silicon Storage Technology, Inc. DS25023A 08/11
18
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Microchip Technology Company
Figure 12:WE# Controlled Chip-Erase Timing Diagram
Figure 13:Software ID Entry and Read
1150 F17.0
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
1150 F09.2
Note: Device ID = D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-byte Sequence for
Software ID Entry
T
WP
T
WPH
T
AA
BF
Device ID
55AA 90