ADM4168E Data Sheet
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
A1
RO1
DE1
B2
A2
RO2
B1
GND
16
15
14
13
12
11
10
9
DI1
Y1
Z1
Y2
DI2
Z2
DE2
V
CC
ADM4168E
TOP VIEW
(Not to Scale)
10820-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 B1 Inverting Receiver Input B, Transceiver 1.
2 A1 Noninverting Receiver Input A, Transceiver 1.
3 RO1 Receiver Output, Transceiver 1.
4 DE1 Driver Output Enable, Transceiver 1. A logic high enables the differential driver outputs, Y1 and Z1; a logic low
places the differential driver outputs in a high impedance state.
5 RO2 Receiver Output, Transceiver 2.
6 A2 Noninverting Receiver Input A, Transceiver 2.
7 B2 Inverting Receiver Input B, Transceiver 2.
8 GND Ground.
9 DI2 Driver Input, Transceiver 2. When the driver is enabled, a logic low on DI2 forces Y2 low and Z2 high, whereas
a logic high on DI2 forces Y2 high and Z2 low.
10 Y2 Noninverting Driver Output Y, Transceiver 2.
11 Z2 Inverting Driver Output Z, Transceiver 2.
12 DE2 Driver Output Enable, Transceiver 2. A logic high enables the differential driver outputs, Y2 and Z2; a logic low
places the differential driver outputs in a high impedance state.
Inverting Driver Output Z, Transceiver 1.
14 Y1 Noninverting Driver Output Y, Transceiver 1.
15 DI1 Driver Input, Transceiver 1. When the driver is enabled, a logic low on DI1 forces Y1 low and Z1 high, whereas
a logic high on DI1 forces Y1 high and Z1 low.
16 V
Power Supply (5 V ± 10%).
