PCI-Express Clock Generator IC,
PLL Core, Dividers, Two Outputs
AD9573
FEATURES
Fully integrated VCO/PLL core
0.54 ps rms jitter from 12 kHz to 20 MHz
Input crystal frequency of 25 MHz
Preset divide ratios for 100 MHz, 33.33 MHz
LVDS/LVCMOS output format
Integrated loop filter
Space saving 4.4 mm × 5.0 mm TSSOP
0.235 W power dissipation
3.3 V operation
APPLICATIONS
Line cards, switches, and routers
CPU/PCIe applications
Low jitter, low phase noise clock generation
GENERAL DESCRIPTION
The AD9573 provides a highly integrated, dual output clock
generator function including an on-chip PLL core that is
optimized for PCI-e applications. The integer-N PLL design
is based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize line
card performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump, a low phase noise
voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider.
By connecting an external 25 MHz crystal, output frequencies
of 100 MHz and 33.33 MHz can be locked to the input reference.
The output divider and feedback divider ratios are prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The AD9573 is available in a 16-lead 4.4 mm × 5.0 mm TSSOP
and can be operated from a single 3.3 V supply. The temperature
range is −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DD × 5
OEGND × 5
AD9573
XTAL
OSC
VCO
PFD/CP
3RD ORDER
LPF
DIVIDERS
LDO
100MHz
LVDS
LVCMOS
33.33MHz
07500-001
Figure 1.
Rev. 0
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