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DDF18C128x72H.fm - Rev. B 10/07 EN
8 ©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, DR) 200-Pin DDR SDRAM SODIMM
I
DD
Specifications
IDD Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in I
DD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 8: IDD Specifications and Conditions – 1GB
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335
-26A/
-265 Units
Operating one bank active-precharge current:
One device
bank; Active-precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two clock cycles
IDD0
1
1,440 1,215 1,080 mA
Operating one bank active-read-precharge current: One
device bank; Active-read precharge; BL = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1
1
1,710 1,485 1,350 mA
Precharge power-down standby current: All device banks
idle; Power-down mode;
t
CK =
t
CK (MIN); CKE = (LOW)
IDD2P
2
90 90 90 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control
inputs
changing once per clock cycle; V
IN
= V
REF
for DQ, DQS,
and DM
IDD2F
2
990 810 720 mA
Active power-down standby current: One device bank
active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD3P
2
810 630 540 mA
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank; Active-precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once
per clock cycle
IDD3N
2
1,080 900 810 mA
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN); IOUT = 0mA
IDD4R
1
1,755 1,530 1,350 mA
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
IDD4W
1
1,800 1,320 1,260 mA
Auto refresh current
t
REFC =
t
RFC (MIN)
IDD5
2
6,210 5,220 5,040 mA
t
REFC = 7.8125µs
IDD5A
2
198 180 180 mA
Self refresh current: CKE ≤ 0.2V
IDD6
2
90 90 90 mA
Operating bank interleave read current: Four device bank
interleaving reads; (BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs
change only during active READ or WRITE commands
IDD7
1
4,095 3,690 3,195 mA
