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STA1085EOATR

P1-P3P4-P6P7-P9P10-P12P13-P13
System description STA1080, STA1085, STA1090, STA1095
4/13 DocID028279 Rev 1
2 System description
2.1 Processor MCU
Accordo2 family devices processing capability relies on an ARM Cortex-R4. The MCU has
instruction cache and data cache, as well as TCM Memory dedicated respectively to
instructions and data for high throughput and low latency tasks.
2.2 Memory controller
2.2.1 Embedded memory
Accordo2 family devices embed SRAM memory, which can be used for data or code
storage.
Embedded memory can be used in conjunction with executable in place NOR devices to
implement cost effective solutions. The whole embedded memory is also cacheable and
can be accessed by DMA.
2.2.2 SDRAM controller
SDRAM controller supports SDRAM JEDEC interface 16 bits wide, which allows interfacing
to automotive SDRAM memory devices to handle high footprint applications.
Such memory is cacheable, and can be accessed by DMA.
2.2.3 SQI executable in place
The SQIO controller allows interfacing Serial Quad I/O flash memories.
2.2.4 Parallel memory interface
FSMC static memory controller, provides a generic parallel interface suitable to connect to
NOR devices as well as SRAM and NAND devices. This peripheral allows execution in-
place from NOR/SRAMs, as well as DMA accesses.
NOR memory space can be partitioned so to reserve a portion of the parallel NOR device to
the Secure CAN Subsystem.
2.3 USB
Accordo2 family devices have one USB HS interface with embedded PHY, allowing to
efficiently connect to mass storage devices, as well as portable devices (phones, pads).
Along with USB connectivity, Accordo2 family fully support USB charger specification.
2.4 Sound subsystem
Accordo2 family devices implement a sound subsystem which allows to efficiently handle
sound processing tasks, such as spatialization and equalizer, without loading the main CPU
with interrupt intensive tasks.
DocID028279 Rev 1 5/13
STA1080, STA1085, STA1090, STA1095 System description
13
2.4.1 Audio interfaces
A complete set of audio interfaces is provided, in order to simplify integration with amplifiers,
and input sources. Each interface can be routed to the sound subsystem. A complete list of
audio interfaces is provided below:
Audio ADC
– Shared between AUX LINE and TUNER LINE
– ADC Inputs are single ended 3.3 V
Voice ADC
– Shared among Voice and TEL-IN lines with embedded multiplexer
– Both Mic and Tel-In lines are differential inputs
Stereo DAC
Multiple I2S IN
Multiple I2S OUT
SPDIF IN for CD/CDROM input with Hardware Block Decoder for CDROM error
correction.
2.4.2 Routing and sample rate converters
Each audio interface can be routed in both directions (IN/OUT) through hardware sample
rate converters, which allow normalizing the sampling rate to the sound processing engine.
The audio routing infrastructure is designed to deliver high quality sample rate conversion
on multiple channels, allowing simultaneous audio streams, such as Bluetooth® Hands
Free and audio media playback, to be handled without CPU load.
2.4.3 Sound DSP
Accordo2 family devices are equipped with multiple DSPs dedicated to sound processing,
fully integrated with the sound subsystem with a specific isochronous bus. DSP is provided
with an integrated sound processing library implementing effects like spatialization,
balancing and equalizer, etc..
2.5 SDMMC
Accordo2 family devices are equipped with SDMMC controllers, which allow interfacing to
either mass storage devices, or to Wi-Fi modules.
2.6 DMA
DMA is designed to efficiently perform memory to memory, and memory to peripherals
transfers, offloading such tasks from the processor, thus reducing interrupt handling load.
DMA provides independent channels which can be dynamically assigned to different data-
path. Complex Scatter/gather transfers can be implemented by programming specific DMA
command linked lists.
System description STA1080, STA1085, STA1090, STA1095
6/13 DocID028279 Rev 1
2.7 Secure CAN subsystem
Accordo2 family devices allow isolating critical code from main application by implementing
a dedicated subsystem based on ARM Cortex-M3, along with:
256 KB dedicated embedded SRAM
Dedicated embedded SRAM
CAN controller
Dedicated GPIOs
In order to guarantee security of CAN network, it can be completely isolated from the rest of
the system, in such a way that no application running on Cortex-R4 can access by any
mean to CAN specific resources. The secure sub-system communicates with the
application running on Cortex-R4 using a Hardware Mailbox interrupt based mechanism.
A specific set of peripherals can be reserved and locked to be only accessible from
CortexM3, thus allowing a complete independent subsystem. In addition to that, specific
secure GPIOs as well as wake signals are reserved to such system.
2.8 General purpose ADC
Accordo2 family devices have general purpose ADCs with a resolution of 10-bits.
2.9 GPIOs
Accordo2 family devices have GPIOs which can be independently configured either as
INPUT or OUTPUT. In order to make the system flexible, these IOs are multiplexed on PINs
with other peripherals.
2.10 Generic interfaces
2.10.1 UARTS
Programmable baud rates up to3Mbps
Hardware Flow control
DMA capability
2.10.2 I
2
Cs
Master/slave modes in multi-master environment
Multiple baud rates supported: 100/400/1000/3400 Kbits/s
DMA capability
P1-P3P4-P6P7-P9P10-P12P13-P13

STA1085EOATR

Mfr. #:
Buy STA1085EOATR
Manufacturer:
STMicroelectronics
Description:
Audio DSPs Accordo2 Dual Core CortexR4/CortexM3 processor, with embedded SRAM, integrated DSP sound subsystem, audio ADCs and DACs, isolated CAN MCU for car radio applications
Lifecycle:
New from this manufacturer.
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