S70GL02GP11FAIR10

S70GL02GP
Document Number: 002-01338 Rev. *D Page 7 of 11
2.2 LSE064—64 ball Fortified Ball Grid Array, 13 11 mm
Figure 2.2 LSE064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm
3611 \ 16-038.15 \ 11.13.6
PACKAGE LSE 064
JEDEC N/A
D x E 13.00 mm x 11.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.40 PROFILE
A1 0.40 --- --- BALL HEIGHT
A2 0.79 --- 0.91 BODY THICKNESS
D 13.00 BSC. BODY SIZE
E 11.00 BSC. BODY SIZE
D1 7.00 BSC. MATRIX FOOTPRINT
E1 7.00 BSC. MATRIX FOOTPRINT
MD 8 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
n 64 BALL COUNT
Øb 0.50 0.60 0.70 BALL DIAMETER
eE 1.00 BSC. BALL PITCH
eD 1.00 BSC BALL PITCH
SD / SE 0.50 BSC. SOLDER BALL PLACEMENT
--- DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95,
SECTION 4.3, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
S70GL02GP
Document Number: 002-01338 Rev. *D Page 8 of 11
3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 2.
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA001-SA2046) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the
pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 3 provides the device identification codes for the S70GL02GP. For more information on the autoselect function, refer to the
S29GL01P datasheet.
5. Erase And Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V
CC
, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, V
CC
= 3.0 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
Table 2. S70GL02GP Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range Address Range (16-bit) Notes
64 Kword/128 Kb 2048
SA00 0000000h–000FFFFh Sector Starting Address
: :
SA2047 7FF0000H–7FFFFFFh Sector Ending Address
Table 3. Autoselect Addresses in System
Description Address Read Data (word/byte mode)
Manufacturer ID (Base) + 00h xx01h/1h
Device ID, Word 1 (Base) + 01h 227Eh/7Eh
Device ID, Word 2 (Base) + 0Eh 2248h/48h
Device ID, Word 3 (Base) + 0Fh 2201h/01h
Secure Device Verify (Base) + 03h
For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
Sector Protect Verify (SA) + 02h xx01h/01h = Locked, xx00h/00h = Unlocked
Table 4. Erase And Programming Performance
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.5 3.5 sec
Excludes 00h programming
prior to erasure (Note 3)
Chip Erase Time S70GL02GP 1024 4096 sec
Total Write Buffer Time, for 64 bytes 480 µs
Excludes system level
overhead (Note 4)
Total Accelerated Write Buffer Programming Time,
for 64 bytes
432 µs
Chip Program Time S70GL02GP 1968 sec
S70GL02GP
Document Number: 002-01338 Rev. *D Page 9 of 11
6. BGA Package Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter Symbol Parameter Description Test Setup Typ Max Unit
C
IN
Input Capacitance V
IN
= 0 12 20 pF
C
OUT
Output Capacitance V
OUT
= 0 20 24 pF
C
IN2
Control Pin Capacitance V
IN
= 0 16 20 pF
RESET#, WP#/ACC Separated Control Pin V
IN
= 0 84 90 pF
CE# Separated Control Pin V
IN
= 0 44 50 pF

S70GL02GP11FAIR10

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
NOR Flash Nor
Lifecycle:
New from this manufacturer.
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