PRODUCT BRIEF PRELIMINARY CHL8112A/B
DIGITAL MULTI-PHASE BUCK CONTROLLER
Trademarks and registered trademarks are the property of the respective
owners.
PB0012 Rev. 0.04, August 25, 2010
One Highwood Drive, Tewksbury, MA 01876
Tel: +1(978)-640-0011
www.chilsemi.com
© 2010 CHiL Semiconductor Corp. All rights reserved
FEATURES
5-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
AMD® SVI/G34 & Memory MPoL modes
Dual OCP support for I-spike enhanced AMD CPUs
SMB_Alert Pin for Servers
PMBus Address pin or Variable Gate Drive (CHL8112A)
2nd Temperature Sense (CHL8112B)
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per phase
CHiL Efficiency Shaping Features including Variable
Gate Drive (CHL8112A only), Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads and
Active Diode Emulation for Very Light Loads
CHiL Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Designed for use with coupled inductors
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both loops
Non-Volatile Memory (NVM) for custom configuration
Compatible with CHiL ATL and 3.3V tri-state Drivers
+3.3V supply voltage; 0ºC to 85ºC ambient operation
Pb-Free, RoHS, 6x6 40 pin QFN package
DESCRIPTION
The CHL8112A/B are dual-loop digital multi-phase buck
controllers that drive up to 5 phases. The CHL8112A/B is
fully AMD® SVI compliant on both loops and provides a Vtt
tracking function for DDR memory.
NVM storage saves pins and enables a small package size.
The CHL8112A/B includes the CHiL Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. CHiL Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. CHiL Dynamic Phase Control
adds/drops active phases based upon load current. The
CHL8112A/B can be configured to enter 1-phase operation
and active diode emulation mode automatically or by
command.
CHiL’s unique Adaptive Transient Algorithm (ATA), based
on proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors. In addition, a coupled inductor mode,
with phases added/dropped in pairs, enables further
improvement in transient response and form factor.
The I2C/PMBus interface can communicate with up to 16
CHL8112A/B based VR loops. Device configuration and
fault parameters are easily defined using the CHiL Intuitive
Power Designer (IPD) GUI and stored in on-chip NVM.
The CHL8112A/B provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal.
The CHL8112A/B also includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its “set-and-forget” methodology.
SMB_DIO
PWM5
ENABLE
VRTN
RCSM
ISEN5
ISEN4
ISEN3
VSEN
SMB_CLK
PWM4
VR_READY
1
/
PWRGD
2
IRTN3
IRTN4
IRTN5
RCSP
TSEN
VR_HOT#
1
/
VRHOT_ICRIT#
2
PWM3
SMB_ALERT#
V18A
RRES
VCC
ISEN2
ISEN1
IRTN1
IRTN2
PWM2
PWM1
RCSM_L2
RCSP_L2
VAR_GATE_PM_ADDR (CHL8112A)
TSEN2 (CHL8112B)
NC
1
/ SVD
2
NC
1
/ SVC
2
NC
1
/ VFIXEN
2
VR_READY_L2
1
/ PWROK
2
VCC
VINSEN
VRTN_L2
VSEN_L2
1
2
7
8
5
6
3
4
10
9
30
29
24
23
26
25
28
27
21
22
41 GND
CHL8112A/B
40 Pin 6x6 QFN
Top View
12 1614 1913 1715 201811
39 3537 3238 3436 313340
Notes
1
Pin definition in MPoL mode
2
Pin definition in AMD mode
Figure 1. CHL8112A & CHL8112B Packages
APPLICATIONS
AMD® SVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
